Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

A ManArray processing machine comprising:

• a processing element having Store, Load, MAU, ALU and DSU execution units;
• a 32 bit odd register file having eight read ports and 4 write ports;
• a 32 bit even register file having eight read ports and 4 write ports;
• and
• a plurality of multiplexers to select the odd or even register file or both for a read operation.

A method of operating on double width and single width files utilizing a single reconfigurable register file, the method comprising the following steps:

• configuring a double width file into a most significant bits half (MSBH) and least significant bits half (LSBH);
• storing the MSBH in a first register file;
• storing the LSBH in a second register file;
• and
• utilizing a multiplexer to select the first register file or the second register file or both to perform a read operation.

A reconfigurable register file capable of storing and retrieving double and single width data types on a cycle by cycle basis comprising:

• an odd register file having an associated extended register file;
• an even register file having an associated extended register file;
• a multiplexer to select the odd or the even register file or both for a single width or double width read operation;
• and
• combinatorial logic to select the odd or the even register file or both for a single width or double width write operation.

A ManArray processing machine comprising:

• a processing element having Store, Load, MAU, ALU and DSU execution units;
• a p-bit odd register file having at least 8 read ports and at least 4 write ports;
• a p-bit even register file having at least 8 read ports and at least 4 write ports;
• and
• a plurality of multiplexers to select the odd or even register file for a read operation.

A VLIW ManArray processing machine comprising:

• a processing element having multiple execution units;
• a p-bit odd register file having q-read ports and r-write ports;
• a p-bit even register file having q-read ports and r-write ports;
• and
• a plurality of multiplexers to select the odd or even register file for a read operation.

A reconfigurable register file apparatus having extended precision comprising:

• at least two x/2-bit registers;
• at least two extended precision registers;
• a multiplier for performing x/2 times x/2 multiply operations on x/2-bit numbers from two of said at least two x/2-bit registers to produce an x-bit result;
• an extended accumulator for extending the x-bit result;
• and
• a multiplexer for selecting one of the at least two extended precision registers for storage of a partial sum of product value for a next multiply accumulate operation.