Method and apparatus for efficient clearing of memory

A method for clearing memory, the method comprises the steps of:

• a) representing a group of memory locations by a representative value, wherein the memory includes a plurality of groups of memory locations;
• b) when the representative value is in a first state, storing a clear value in each corresponding memory location of a cache memory, wherein the corresponding memory locations of the cache memory correspond to the group of memory locations;
• c) when the representative value is in a second state, reading data from the group of memory locations to the corresponding memory locations of the cache memory;
• and
• d) writing data stored in the corresponding memory locations of the cache memory to the group of memory locations when a cache write back command is received.

A memory system having a fast clear process, the memory system comprises:

• a memory having a first plurality of memory locations, wherein the first plurality of memory locations are grouped into a plurality of groups of memory locations;
• a representative memory having a second plurality of memory locations, wherein each of the second plurality of memory locations is representative of a corresponding one of the plurality of groups of memory locations;
• cache memory that includes at least one line of memory, wherein the one line of memory has storage capacity to store data of a group of memory locations;
• and
• memory controller operably coupled to the memory, the representative memory, and the cache memory, wherein the memory controller causes a clear value to be written into the at least one line of memory of the cache memory when the representative value representing the group of memory locations is in a first state, and wherein the memory controller causes the data of the group of memory locations to be written into the at least one line of memory of the cache memory when the representative value representing the group of memory locations is in a second state.

A memory controller that controls a memory, the memory controller comprises:

• a processing module;
• and
• memory operably coupled to the processing module, wherein the memory stores operating instructions that cause the processing module to (a) represent a group of memory locations by a representative value, wherein the memory includes a plurality of groups of memory locations;
• when the representative value is in a first state:
• (b) store a clear value in each corresponding memory location of a cache memory, wherein the corresponding memory locations of the cache memory correspond to the group of memory locations;
• (c) set a dirty bit for the corresponding memory locations of the cache memory;
• and (d) read data from the group of memory locations to the corresponding memory locations of the cache memory when the representative value is in a second state.

A memory controller that controls a memory, the memory controller comprises:

• a processing module;
• and
• memory operably coupled to the processing module, wherein the memory stores operating instructions that cause the processing module to (a) represent a group of memory locations by a representative value, wherein the memory includes a plurality of groups of memory locations;
• (b) store a clear value in each corresponding memory location of a cache memory when the representative value is in a first state, wherein the corresponding memory locations of the cache memory correspond to the group of memory locations;
• (c) read data from the group of memory locations to the corresponding memory locations of the cache memory when the representative value is in a second state;
• and (d) write data stored in the corresponding memory locations of the cache memory to the group of memory locations when a cache write back command is received.