Data strobe for faster data access from a memory array

A method of accessing a dynamic random access memory (DRAM) array comprising a first DRAM set, a second DRAM set, and a DRAM array output, said method comprising:

• (a) asserting a first column address strobe (CAS) to said first DRAM set;
• (b) asserting a data strobe to a data path coupled to said DRAM array output;
• (c) latching first data on said DRAM array output at the data path based on said data strobe;
• (d) de-asserting said data strobe and said first CAS;
• and
• (e) asserting a second CAS to said second DRAM set.

A memory subsystem for a computer system comprising:

• a memory controller;
• a DRAM memory array coupled to said memory controller and comprising a first DRAM set, a second DRAM set, and a DRAM array output;
• and
• a data path coupled to said memory controller and said DRAM array output;
• wherein said memory controller comprises:
• means for asserting a first column address strobe (CAS) to said first DRAM set;
• means for asserting a data strobe to said data path
• means for latching first data on said DRAM array output at the data path based on said data strobe;
• means for de-asserting said data strobe and said first CAS;
• and
• means for asserting a second CAS to said second DRAM set.

A computer system comprising:

• a processor;
• a memory bus coupled to said processor;
• and
• a memory subsystem coupled to said memory bus, said memory subsystem comprising:
• a memory controller comprising a data strobe generator;
• a dynamic random access memory (DRAM) array coupled to said memory controller;
• and
• a data path coupled to said data strobe generator and said DRAM array.