Method and apparatus for providing intelligent power management
AssigneePhoenix Technologies Ltd.
InventorRONALD BARBEE
Life of this patent
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Abstract
The present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system. The apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory. The stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active. Various embodiments are described.
Claims42
A power management apparatus for a circuit in a processor-based system, comprising:
- a memory to store instruction sequences by which the processor-based system is processed;
- and
- a processor coupled to the memory, wherein the stored instruction sequences cause the processor to:
- (a) determine a system access time of the circuit;
- and (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active.
A power management apparatus for a circuit in a processor-based system, comprising:
- a memory to store instruction sequences by which the processor-based system is processed;
- and
- a processor coupled to the memory, wherein the stored instruction sequences cause the processor to:
- (a) determine a system access time of the circuit;
- and (b) determine if the system access time is greater than a first predetermined value, if so, decreasing the accessibility period of the circuit, during which the circuit is active.
A power management apparatus for a circuit in a processor-based system, comprising:
- a memory to store instruction sequences by which the processor-based system is processed;
- and
- a processor coupled to the memory, wherein the stored instruction sequences cause the processor to:
- (a) determine if an accessibility period of the circuit is greater than a first predetermined value, if so, terminating power supply to the circuit a system access time of the circuit;
- and (b) determine if the circuit is accessed within a predetermined time interval, if so, activating the circuit.
A power management apparatus for a circuit in a processor-based system, comprising:
- a memory to store instruction sequences by which the processor-based system is processed;
- and
- a processor coupled to the memory, wherein the stored instruction sequences cause the processor to:
- (a) determine an operational mode of the circuit;
- (b) operating the circuit at a first predetermined level based on the operational mode of the circuit.
A method for providing power management for a circuit in a processor-based system, comprising:
- determining a system access time of the circuit;
- and
- determining if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit during which the circuit is active.
A method for providing power management for a circuit in a processor-based system, comprising:
- (a) determining a system access time of the circuit;
- and
- (b) determining if the system access time is greater than a first predetermined value, if so, decreasing the accessibility period of the circuit during which the circuit is active.
A method for providing power management for a circuit in a processor-based system, comprising:
- (a) determining if an accessibility period of the circuit is greater than a first predetermined value, if so, terminating power supply to the circuit a system access time of the circuit;
- and
- (b) determining if the circuit is accessed within a predetermined time interval, if so, activating the circuit.
A method for providing power management for a circuit in a processor-based system, comprising:
- (a) determining an operational mode of the circuit;
- and
- (b) operating the circuit at a first predetermined level based on the operational mode of the circuit.
A computer-readable apparatus, comprising:
- a computer-readable medium that stores an instruction sequence which when executed by a processor causes said processor to:
- determine a system access time of the circuit;
- and
- determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit during which the circuit is active.
A computer-readable apparatus, comprising:
- A computer-readable medium that stores an instruction sequence which when execution by a processor causes the processor to:
- (a) determine a system access time of the circuit;
- and
- (b) determine if the system access time is greater than a first predetermined value, if so, decreasing the accessibility period of the circuit, during which the circuit is active.
A computer-readable apparatus, comprising:
- A computer-readable medium that stores an instruction sequence which when executed by a processor causes said processor to:
- (a) determine if an accessibility period of the circuit is greater than a first predetermined value, if so, terminating power supply to the circuit a system access time of the circuit;
- and
- (b) determine if the circuit is accessed within a predetermined time interval, if so, activating the circuit.
A computer-readable apparatus, comprising:
- A computer-readable medium that stores an instruction sequence which when executed by a processor causes the processor to:
- (a) determine an operational mode of the circuit;
- and (b) operating the circuit at a first predetermined level based on the operational mode of the circuit.
Dependencies are inferred from the claim text.