Communication channel and interface devices for bridging computer interface buses

An interface device for interfacing a first peripheral component interconnect (PCI) bus of a first computer system with a second PCI bus of a second computer system, said interface device comprising:

• a first connector for coupling to the first PCI bus;
• a second connector for coupling to the second PCI bus;
• and
• a cable coupled to said first and second connectors, wherein said cable comprises an interface channel including a clock channel on a pair of conductive lines and a plurality of bit channels on a plurality of pairs of conductive lines, for transferring information between said first and second connectors using low voltage differential signals (LVDS).

In a computer system including an attached computer module (ACM) and a peripheral console, an interface device for interfacing a primary peripheral component interconnect (PCI) bus of the ACM to a secondary PCI bus of the peripheral console, said interface device comprising:

• a first connector for coupling to the primary PCI bus;
• a second connector for coupling to the secondary PCI bus;
• and
• an interface channel coupled to said first and second connectors, said interface channel including a clock channel and a plurality of bit channels, wherein said clock channel and said plurality of bit channels are on a plurality of conductive lines and further wherein information is transferred on said interface channel using a protocol different from that of a PCI bus.

An apparatus for interfacing first and second subsystems of a microprocessor based computer system, said apparatus comprising:

• a first computer interface bus within said first subsystem, said first computer interface having a first number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said first computer interface bus operates at a clock speed in a first predetermined clock speed range bounded by a first minimum clock speed and a first maximum clock speed and further wherein each of said bus lines in said first computer interface bus transmits bits in a first predetermined bit rate range bounded by a first minimum per line bit rate and a first maximum per line bit rate;
• a second computer interface bus within said second subsystem, said second computer interface having a second number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said second computer interface bus operates at a clock speed in a second predetermined clock speed range bounded by a second minimum clock speed and a second maximum clock speed and further wherein each of said bus lines in said second computer interface bus transmits bits in a second predetermined bit rate range bounded by a second minimum per line bit rate and a second maximum per line bit rate;
• and
• an interface channel including a clock channel and a plurality of bit channels, wherein said plurality of bit channels are fewer in number than both said first number and said second number.

An apparatus for interfacing first and second subsystems of a microprocessor based computer system, said apparatus comprising:

• a first computer interface bus within said first subsystem, said first computer interface having a first number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said first computer interface bus operates at a clock speed in a first predetermined clock speed range bounded by a first minimum clock speed and a first maximum clock speed;
• a second computer interface bus within said second subsystem, said second computer interface having a second number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said second computer interface bus operates at a clock speed in a second predetermined clock speed range bounded by a second minimum clock speed and a second maximum clock speed;
• and
• an interface channel including a clock channel and a plurality of serial bit channels, wherein each of said plurality of serial bit channels operates at a clock speed higher than both said first maximum clock speed and said second maximum clock speed.

In a computer system having an attached computer module (ACM) and a peripheral console, an apparatus for interfacing the ACM and the peripheral console, said apparatus comprising:

• a first control signal based computer interface bus within the ACM;
• a bit based interface channel coupled to said first control signal based computer interface bus;
• and
• a second control signal based computer interface bus within the peripheral console, said second control signal based computer interface bus coupled to said bit based interface channel.

A computer system comprising:

• an attached computer module (ACM) including a first control based computer interface bus;
• a peripheral console including a second control based computer interface bus;
• and
• a bit based interface channel coupled to said first control signal based computer interface bus and said second control based computer interface device for interfacing said ACM and said peripheral console.

A method of transmitting control signals from a first computer interface bus to a second computer interface bus via a bit based interface channel coupled to the first computer interface bus and the second computer interface bus, said method comprising:

• receiving control signals from the first computer interface bus;
• encoding the control signals received from the first computer interface bus into control bits representing the control signals;
• transmitting the control bits on the bit based interface channel;
• receiving the control bits;
• decoding the control bits into the control signals represented by the control bits;
• and
• transmitting the control signals to the second computer interface bus.