Data transfer control method, and peripheral circuit, data processor and data processing system for the method
AssigneeHitachi, Ltd.
InventorHiroshi Takeda
Life of this patent
Estimating the term…
Abstract
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
Claims13
A method of controlling a data transfer between a data processor and its peripheral circuit, comprising the steps of:
- sending an access request to a peripheral circuit from said data processor;
- allowing said peripheral circuit to perform an internal operation according to the access request in synchronism with the output from a self-excited oscillator incorporated therein and in a manner to understand the content of said access request;
- sending a response request to said peripheral circuit from said data processor in synchronism with its internal operation in response to said access request;
- and
- transferring data to or from said data processor depending on the type of said access request in synchronism with said response request.
A peripheral circuit comprising:
- a cycle timing generator for producing an access cycle signal of an internal operation in response to an access request from a data processor and on the basis of an output of a self-excited oscillator;
- an external terminal for outputting said access cycle signal as a response request in response to said access request;
- and
- an internal timing generator for producing an internal operation timing signal in synchronism with said access cycle signal.
A data processor comprising:
- an access control circuit for sending an access request to a peripheral circuit;
- an input terminal for receiving a response request from the peripheral circuit in response to said access request;
- a buffer memory capable of writing/reading on the basis of said response request and in synchronism with an internal operation clock;
- and
- an arithmetic circuit and an input/output buffer circuit connected with said buffer memory.
A data processor comprising:
- an access control circuit for sending an access request to a peripheral circuit;
- an input terminal for receiving a response request from the peripheral circuit in response to said access request;
- a buffer memory having an asynchronous port for writing/reading on the basis of said response request, and a synchronous port for writing/reading in synchronism with an internal operation clock;
- an arithmetic circuit connected with the synchronous port of said buffer memory;
- and
- an input/output buffer circuit connected with the asynchronous port of said buffer memory for interfacing with external devices.
A data processing system comprising:
- a peripheral circuit that performs an internal operation according to an access request from a data processor and in synchronism with the output of a self-excited oscillator incorporated therein, and outputs a response request to said data processor in synchronism with said internal operation in response to said access request;
- a data processor that sends an access request to a desired peripheral circuit and receives a response request from the desired peripheral circuit, thereby transferring data to or from the peripheral circuit depending on the type of said access request;
- and
- a bus connecting said data processor and said peripheral circuit.
Dependencies are inferred from the claim text.