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US 2001/0010645 A1Published application
Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTomoharu Tanaka, Hiroshi Nakamura, Toru Tanzawa
Life of this patent
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Abstract
A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.
Claims20
A semiconductor memory device comprising:
- memory cells;
- a bitline connected to said memory cells;
- a read circuit including a precharge circuit;
- and
- a first transistor connected between said bitline and said read circuit, wherein
- a first voltage is applied to a gate of said first transistor when said precharge circuit precharges said bitline, and
- a second voltage which is different from the first voltage is applied to said gate of said first transistor when said read circuit senses a change in a voltage of said bitline.
4 more elements
A semiconductor memory device comprising:
- a NAND memory cell unit having a plurality of memory cells connected in series, a first end in which a first select transistor is arranged, and a second end in which a second select transistor is arranged;
- and
- a programming circuit for programming into a selected memory cell among said plurality of memory cells, wherein
- said programming circuit applies, at a time of programming, a first voltage to a gate electrode of said selected memory cell, applies a second voltage which is lower than the first voltage to a gate electrode of a memory cell positioned adjacent at said second end side, to said selected memory cell, and applies a third voltage which is lower than the first voltage but higher than said second voltage to gate electrodes of remaining memory cells of a corresponding NAND memory cell unit.
1 more element
Dependencies are inferred from the claim text.