Data transfer controller, microcomputer and data processing system

A data transfer controller comprising a plurality of data transfer channels respectively having an address register and a control register, an internal bus connected to the address register and control register included in a plurality of said data transfer channels, a bus interface circuit for interfacing said internal bus with an external bus and a control circuit for executing transfer control using only one data transfer channel of a plurality of said data transfer channels via said bus interface circuit depending on the data transfer request;

• wherein
• said address register is provided with a data transfer source address and a data transfer destination address;
• said control register has a storing area for the resource select information to designate with a plurality of bits the combination mode of a data transfer request source, a data transfer source responding to the data transfer request from such request source and a data transfer destination assigned to the data transfer channel including the relevant control register;
• an address error detector section is provided to detect an address error in which at least one of the data transfer source address and the data transfer destination address set to said address register is deviated from the combination mode of the data transfer source and data transfer destination designated by said resource select information included in said control register of the relevant data transfer channel;
• and
• said control circuit determines the data transfer channel to respond to the request source, when a data transfer request is detected, from the resource select information set to said control register and executes the data transfer operation using the data transfer channel depending on said data transfer request under the condition that said address error is not detected.

A data transfer controller comprising:

• a plurality of data transfer channels respectively having an address register and a control register;
• an operation register used in common to a plurality of said data transfer channels;
• an internal bus connected to the address register and control register included in a plurality of said data transfer channels and said operation register, an interface circuit for interfacing said internal bus with the external circuits;
• and a control circuit for executing the control operation via said bus interface circuit using one data transfer channel among a plurality of said data transfer channels depending on the data transfer request;
• wherein
• said address register is provided for setting the data transfer source address and data transfer destination address;
• said control register has a storing area for the resource select information to designate the combination mode of the data transfer request source, the data transfer source responding to the data transfer request from the request source and the data transfer destination assigned to the data transfer channel including the relevant control register and the data transfer destination;
• said operation register is provided, when the data transfer requests are competing, for setting the priority of the data transfer channel to execute the data transfer requests and comprises an address error detector section for detecting an address error when at least any one of the data transfer source address and data transfer destination address set to said address register is deviated from the combination mode of the data transfer source and data transfer destination designated by said resource select information of said data transfer channel;
• and
• said control circuit determines, when a data transfer request is generated, the data transfer channel to respond to such request from said resource select information and also determines, when the data transfer requests for a plurality of said data transfer channels are competing, one data transfer channel responding to the data transfer request by setting the priority to the data transfer request to the data transfer channel having the higher priority being set to said operation register in order to execute the data transfer using said determined data transfer channel under the condition that said address error is not detected.

A data processing system comprising:

• a central processing unit;
• an address register to which a data transfer source address and a data transfer destination address are set by said central processing unit;
• a control register including a storing area for the resource select information for designating with a plurality of bits the combination mode of the data transfer source and data transfer destination;
• an address error detector section for detecting an address error in which at least one of said data transfer source address and data transfer destination address set to said address register is deviated, when a data transfer request is detected, from the combination mode of the data transfer source and data transfer destination designated by said resource select information of said control register;
• and
• a control circuit for executing, when said address error is not detected, the data transfer control utilizing information of said address register and control register and controlling, when said address error is detected, the data transfer control responding to said data transfer request.