High performance sub-system design and assembly

An interchip interface circuit formed in multiples upon a first and second integrated circuit chip for communication between internal circuits of the first and second integrated circuit chip;

• whereby said first integrated circuit chip is attached physically and electrically to said second integrated circuit chip;
• and
• whereby said interchip interface circuit comprises:
• an internal interface circuit for transferring electrical signals between the second integrated circuit chip to the first integrated circuit chip;
• a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry of one of the integrated circuit chip, a third terminal connected to test circuits, and a control terminal;
• and
• a mode selector connected to the control terminal to selectively connect the output of the internal interface circuit to the internal circuitry of the integrated circuit chips during normal operation and the output of the internal interface circuit to the test circuitry during testing procedures.

A method of forming a multiple integrated circuit chip structure comprising the steps of:

• simultaneously but separately forming internal circuits on a first semiconductor wafer containing a plural first integrated circuit chip and a second semiconductor wafer containing a plural second integrated circuit chip;
• simultaneously forming test circuits on the first wafer and the second wafer;
• simultaneously forming interchip interface circuits on the first wafer and the second wafer, whereby forming said interchip interface circuit comprises the steps of:
• forming an internal interface circuit for transferring electrical signals between the second integrated circuit chip to the first integrated circuit chip;
• forming a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry of the first integrated circuit chip;
• forming a mode selector to selectively connect the output of the internal interface circuit to the internal circuitry of the first integrated circuit chip during normal operation and the output of the internal interface circuit to the test circuitry during test and burn-in;
• forming input/output interface circuits on said second wafer;
• contacting, stimulating, and examining a response of the test circuits on the first wafer and the test circuits and input/output interface circuits on the second wafer;
• separating the first wafer into a plurality of separated first integrated circuit chips;
• contacting with sockets, stimulating and burning-in the plurality of separated first integrated circuit chips for an extended period of time;
• contacting, stimulating, and examining the plurality of separated first integrated circuit chips;
• discarding defective first integrated circuit chips;
• attaching each functioning chip of the first integrated circuit chips to one of one functioning second integrated circuit chip on the second wafer
• separating the second wafer into the plurality of second integrated circuit chips;
• and
• contacting the input/output interface circuits, stimulating, and examining the response of the formed multiple integrated circuit chip structure.