# US 12,772,906 B2 · Packaging structure and packaging method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,906 B2 - Document ID: US12772906B2 - Status: Granted - Kind: B2 - Application number: 18/374,140 - Filed: 2023-09-28 - Published: 2024-05-30 - Granted: 2026-10-20 - Earliest claimed: 2022-11-24 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation - Inventors: Jisong Jin - Web page: https://patentgrep.com/patent/US12772906B2 ## CPC - H10W 90/00: Package configurations - H10W 70/093 - H10W 70/095: {of vias therein} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side, and a first interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier; forming a first packaging layer covering a side wall of the device chip and filling between device chips on the carrier; providing an interconnect chip, a second interconnection structure being formed on the interconnect chip, and the second interconnection structure exposing a surface of the interconnect chip; bonding the interconnect chip to the device chip and the first packaging layer, the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip; and forming a second packaging layer covering the interconnect chip on the first packaging layer. ## Claims ### Claim 1 A packaging structure, comprising: a plurality of device chips, where a device chip of the plurality of device chips comprises a first side and a second side facing away from the first side, and a first interconnection structure being formed on the first side of the device chip; a first packaging layer, covering a side wall of the device chip and filling between device chips of the plurality of device chips, the first packaging layer exposing the first side of the device chip; an interconnect chip, bonded to the device chip and the first packaging layer, a second interconnection structure being formed on the interconnect chip, the second interconnection structure being exposed from a surface of the interconnect chip, and the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip; and a second packaging layer, located on the first packaging layer and covering the interconnect chip. ### Claim 2 (depends on 1) The packaging structure according to claim 1, wherein the first side is a front side of the device chip, and the second side is a back side of the device chip. ### Claim 3 (depends on 1) The packaging structure according to claim 1, wherein a plurality of first interconnection structures being formed in the device chip. ### Claim 4 (depends on 1) The packaging structure according to claim 1, wherein the packaging structure further comprises: a via interconnection structure, running through the second packaging layer and electrically connected to the device chip. ### Claim 5 (depends on 4) The packaging structure according to claim 4, wherein another first interconnection structure is formed on the device chip, and a via interconnection structure runs through the second packaging layer on a top of the another first interconnection structure exposed by the interconnect chip and contacts the another first interconnection structure. ### Claim 6 (depends on 5) The packaging structure according to claim 5, wherein the packaging structure further comprises: a connection layer, located in the second packaging layer on a top of the via interconnection structure and extending along a direction parallel to the second packaging layer; and a conductive bump, located on the connection layer. ### Claim 7 (depends on 5) The packaging structure according to claim 5, wherein the packaging structure further comprises: a redistribution structure, located on the second packaging layer and the via interconnection structure; and a conductive bump, located on the redistribution structure. ### Claim 8 (depends on 7) The packaging structure according to claim 7, wherein the redistribution structure comprises one or more redistribution layers. ### Claim 9 (depends on 1) The packaging structure according to claim 1, wherein a first dielectric layer is formed on the first side of the device chip, a first top layer line is formed in the first dielectric layer, and the first interconnection structure runs through the first dielectric layer above the first top layer line and contacts the first top layer line. ### Claim 10 (depends on 1) The packaging structure according to claim 1, wherein a first dielectric layer is formed on the first side of the device chip, a first pad is formed in the first dielectric layer, and the first interconnection structure is located in the first dielectric layer on a top of the first pad. ### Claim 11 (depends on 1) The packaging structure according to claim 1, wherein a second dielectric layer is formed on the interconnect chip, a second top layer line is formed in the second dielectric layer, and the second interconnection structure runs through the second dielectric layer above the second top layer line and contacts the second top layer line. ### Claim 12 (depends on 1) The packaging structure according to claim 1, wherein a second dielectric layer is formed on the interconnect chip, a second pad is formed in the second dielectric layer, and the second interconnection structure is located in the second dielectric layer on a top of the second pad. ### Claim 13 (depends on 1) The packaging structure according to claim 1, wherein a material of the first interconnection structure comprises at least one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium, and a material of the second interconnection structure comprises at least one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.