# US 12,772,865 B2 · Multi-level bridge interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,865 B2 - Document ID: US12772865B2 - Status: Granted - Kind: B2 - Application number: 17/134,601 - Filed: 2020-12-28 - Published: 2022-06-30 - Granted: 2026-10-20 - Earliest claimed: 2020-12-28 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Rahul Agarwal; Raja Swaminathan - Web page: https://patentgrep.com/patent/US12772865B2 ## CPC - H10W 70/093 - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor device, including: bonding a first chip layer comprising a first semiconductor chip to a second chip layer comprising a second semiconductor chip to electrically couple an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; and bonding a third chip layer comprising a third semiconductor chip to the second chip layer to electrically couple an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising: bonding a first semiconductor chip to a second semiconductor chip, the first semiconductor chip being stacked on the second semiconductor chip; bonding a third semiconductor chip to the second semiconductor chip, the second semiconductor chip being stacked on the third semiconductor chip, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are arranged such that a back side of the first semiconductor chip faces a front side of the second semiconductor chip, and a back side of the second semiconductor chip faces a front side of the third semiconductor chip; wherein at least one interconnect of the second semiconductor chip comprises a first through silicon via electrically coupling the back side of the second semiconductor chip to the front side of the second semiconductor chip, and wherein the first through silicon via extends to the back side of the second semiconductor chip to be coplanar with a back side surface of the second semiconductor chip and is not coplanar with a front side surface of the second semiconductor chip; and wherein at least one interconnect of the first semiconductor chip comprises a second through silicon via electrically coupling the back side of the first semiconductor chip to the front side of the first semiconductor chip, and wherein the second through silicon via extends to the back side of the first semiconductor chip to be coplanar with a back side surface of the first semiconductor chip and is not coplanar with a front side surface of the first semiconductor chip. ### Claim 2 (depends on 1) The method of claim 1, wherein: bonding the first semiconductor chip to the second semiconductor chip electrically couples an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; bonding the third semiconductor chip to the second semiconductor chip electrically couples an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip; an interconnect chip is laterally adjacent to the first semiconductor chip; and bonding the first semiconductor chip to the second semiconductor chip also electrically couples a first interconnect of the interconnect chip to a third interconnect of the second semiconductor chip and a second interconnect of the interconnect chip to a first interconnect of a fourth semiconductor chip. ### Claim 3 (depends on 2) The method of claim 2, wherein a second interconnect chip is laterally adjacent to the third semiconductor chip, wherein the interconnect chip and the second interconnect chip each include internal conductor traces for routing communications between semiconductor chips, and wherein bonding the third semiconductor chip to the second semiconductor chip electrically couples a first interconnect of the second interconnect chip to a fourth interconnect of the second semiconductor chip and a second interconnect of the second interconnect chip to a second interconnect of the fourth semiconductor chip. ### Claim 4 (depends on 1) The method of claim 1, wherein: bonding the first semiconductor chip to the second semiconductor chip electrically couples an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; bonding the third semiconductor chip to the second semiconductor chip electrically couples an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip; and the method further comprises electrically coupling the interconnect of the first semiconductor chip and the first interconnect of the second semiconductor chip by way of a redistribution layer. ### Claim 5 A semiconductor device comprising: a first chip layer comprising a first semiconductor chip having a plurality of interconnects; a second chip layer comprising a second semiconductor chip having a plurality of interconnects; a third chip layer comprising a third semiconductor chip having a plurality of interconnects, wherein the first semiconductor chip is stacked on the second semiconductor chip, wherein the second chip layer is stacked on the third chip layer, and wherein the first chip layer, the second chip layer, and the third chip layer are arranged such that a back side of the first semiconductor chip faces a front side of the second semiconductor chip, and a back side of the second semiconductor chip faces a front side of the third semiconductor chip; wherein at least one interconnect of the second semiconductor chip comprises a first through silicon via electrically coupling the back side of the second semiconductor chip to the front side of the second semiconductor chip, and wherein the first through silicon via extends to the back side of the second semiconductor chip to be coplanar with a back side surface of the second semiconductor chip and is not coplanar with a front side surface of the second semiconductor chip; and wherein at least one interconnect of the first semiconductor chip comprises a second through silicon via electrically coupling the back side of the first semiconductor chip to the front side of the first semiconductor chip, and wherein the second through silicon via extends to the back side of the first semiconductor chip to be coplanar with a back side surface of the first semiconductor chip and is not coplanar with a front side surface of the first semiconductor chip. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein: a first interconnect of the first semiconductor chip is electrically coupled to a first interconnect of the second semiconductor chip; a first interconnect of the third semiconductor chip is electrically coupled to a second interconnect of the second semiconductor chip; and the first chip layer further comprises an interconnect chip laterally adjacent to the first semiconductor chip and having a plurality of interconnects, the second chip layer further comprises a fourth semiconductor chip having a plurality of interconnects, and a first interconnect of the interconnect chip is electrically coupled to a third interconnect of the second semiconductor chip and a second interconnect of the interconnect chip is electrically coupled to a first interconnect of the fourth semiconductor chip. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the third chip layer further comprises a second interconnect chip laterally adjacent to the third semiconductor chip and having a plurality of interconnects, wherein the interconnect chip and the second interconnect chip each include internal conductor traces for routing communications between semiconductor chips, and wherein a first interconnect of the second interconnect chip is electrically coupled to a fourth interconnect of the second semiconductor chip and a second interconnect of the second interconnect chip is electrically coupled to a second interconnect of the fourth semiconductor chip. ### Claim 8 (depends on 5) The semiconductor device of claim 5, wherein: a first interconnect of the first semiconductor chip is electrically coupled to a first interconnect of the second semiconductor chip; a first interconnect of the third semiconductor chip is electrically coupled to a second interconnect of the second semiconductor chip; and the semiconductor device further comprises a redistribution layer electrically coupling the first interconnect of the first semiconductor chip and the first interconnect of the second semiconductor chip. ### Claim 9 A method of manufacturing a semiconductor device, comprising: mounting a first semiconductor chip, a second semiconductor chip, and a first interconnect chip together to form a first chip layer, wherein the first semiconductor chip, the second semiconductor chip, and the first interconnect chip each have a plurality of interconnects with at least one interconnect comprising a thru silicon via electrically coupling a substrate portion of a respective semiconductor chip to an interconnect portion of the respective semiconductor chip; bonding a third semiconductor chip and a fourth semiconductor chip to the first chip layer to form a second chip layer, wherein the third semiconductor chip and the fourth semiconductor chip each have a plurality of interconnects with at least one interconnect comprising a thru silicon via electrically coupling a substrate portion of a respective semiconductor chip to an interconnect portion of the respective semiconductor chip, wherein a first interconnect of the first semiconductor chip is coupled to a first interconnect of the third semiconductor chip, and a first interconnect of the first interconnect chip is electrically coupled to a second interconnect of the third semiconductor chip, and wherein a second interconnect of the first interconnect chip is electrically coupled to a first interconnect of the fourth semiconductor chip, and a first interconnect of the second semiconductor chip is electrically coupled to a second interconnect of the fourth semiconductor chip; and bonding a fifth semiconductor chip, a sixth semiconductor chip, and a second interconnect chip to the second chip layer to form a third chip layer, wherein the fifth semiconductor chip, the sixth semiconductor chip, and the second interconnect chip each have a plurality of interconnects, wherein a third interconnect of the second semiconductor chip is coupled to a first interconnect of the fifth semiconductor chip, and a fourth interconnect of the second semiconductor chip is electrically coupled to a first interconnect of the second interconnect chip, and wherein a third interconnect of the fourth semiconductor chip is electrically coupled to a second interconnect of the second interconnect chip, and a fourth interconnect of the fourth semiconductor chip is electrically coupled to a first interconnect of the sixth semiconductor chip. ### Claim 10 (depends on 9) The method of claim 9, wherein the first chip layer is bonded to a carrier, and wherein the method further comprises bonding a support wafer to the third chip layer and removing the carrier. ### Claim 11 (depends on 9) The method of claim 9, wherein the method further comprises filling gaps between the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, and the fifth semiconductor chip with a gap fill material. ### Claim 12 (depends on 9) The method of claim 9, further comprises forming a plurality of through die vias providing access to the second chip layer. ### Claim 13 (depends on 9) The method of claim 9, further comprising bonding a substrate portion of the first chip layer to a carrier and bonding a support wafer to the third chip layer. ### Claim 14 (depends on 9) The method of claim 9, further comprising including a redistribution layer between the first chip layer and the second chip layer. ### Claim 15 (depends on 1) The method of claim 1, wherein the front side includes one or more layers of metallization and interlevel dielectric materials. ### Claim 16 (depends on 1) The method of claim 1, wherein the front side includes: a physical device region having conductive structures for transmission of chip-to-chip signals; and a non-physical device region having conductive structures for transmission of one or more of power signals, ground signals, or chip-to-circuit board signals. ### Claim 17 (depends on 5) The semiconductor device of claim 5, wherein the front side includes one or more layers of metallization and interlevel dielectric materials. ### Claim 18 (depends on 8) The semiconductor device of claim 8, wherein the front side includes: a physical device region having conductive structures for transmission of chip-to- chip signals; and a non-physical device region having conductive structures for transmission of one or more of power signals, ground signals, or chip-to-circuit board signals. ### Claim 19 (depends on 3) The method of claim 3, wherein a fifth semiconductor chip is laterally adjacent to the interconnect chip, and wherein bonding the first semiconductor chip to the second semiconductor chip also electrically couples a first interconnect of the fifth semiconductor chip to a third interconnect of the fourth semiconductor chip. ### Claim 20 (depends on 19) The method of claim 19, wherein a sixth semiconductor chip is laterally adjacent to the second interconnect chip, and wherein bonding the third semiconductor chip to the second semiconductor chip electrically couples a first interconnect of the sixth semiconductor chip to a fourth interconnect of the fourth semiconductor chip.