# US 12,772,858 B2 · Semiconductor device with improved ESD performance, ESD reliability and substrate embedded powergrid approach > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,858 B2 - Document ID: US12772858B2 - Status: Granted - Kind: B2 - Application number: 17/950,175 - Filed: 2022-09-22 - Published: 2024-01-25 - Granted: 2026-10-20 - Earliest claimed: 2022-07-25 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Aruldas Divakaran; Subramanian Narasimhamoorthy; Mallikarjungouda S Patil - Web page: https://patentgrep.com/patent/US12772858B2 ## CPC - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/427: {Power or ground buses} - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a substrate, a plurality of metal rails embedded in the substrate, and a power grid embedded in the substrate, at least one of the plurality of metal rails being part of the power grid and being directly connected to the substrate to control an Electrostatic Discharge (ESD) in the semiconductor device. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; an electrostatic discharge (ESD) device including a diode and configured to control an electrostatic discharge in the semiconductor device; a plurality of metal rails embedded within the substrate; and a power grid embedded within the substrate, at least one of the plurality of metal rails being part of the power grid and being directly connected to the ESD device, wherein the plurality of metal rails are buried in the substrate below a top surface of the substrate, and wherein the ESD device is disposed on and overlaps a buried portion of the power grid in a direction perpendicular to the top surface of the substrate. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein at least one of the plurality of metal rails is a heat sink in the semiconductor device. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, further comprising at least one trench embedded in the substrate, the at least one of the plurality of metal rails being embedded in the at least one trench. ### Claim 4 (depends on 3) The semiconductor device as claimed in claim 3, wherein a thickness of the at least one trench is larger than a width of the at least one trench. ### Claim 5 (depends on 3) The semiconductor device as claimed in claim 3, wherein a depth of the at least one trench is controlled to modify a capacitance value in the semiconductor device. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, further comprising at least one decoupling capacitance part integrated with at least two of the plurality of metal rails in the power grid to provide a high signal integrity and high density routing. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, further comprising at least one decoupling capacitance part between adjacent ones of the plurality of metal rails, the at least one decoupling capacitance part being embedded inside the substrate. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: at least two through-silicon vias (TSVs) connected with the power grid at two sides of the semiconductor device; at least one decoupling capacitance part in the power grid, the at least one decoupling capacitance part being embedded in the substrate between power lines; and a standard cell on at least one of the power lines. ### Claim 9 (depends on 8) The semiconductor device as claimed in claim 8, wherein the at least two TSVs are between the plurality of metal rails in the power grid. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: at least one decoupling capacitance part between a power line and a ground line in the power grid; and a standard cell on the power line. ### Claim 11 (depends on 10) The semiconductor device as claimed in claim 10, wherein the at least one decoupling capacitance part includes a high-k dielectric part, the high-k dielectric part being between the power line and the ground line and defining a capacitor. ### Claim 12 (depends on 10) The semiconductor device as claimed in claim 10, wherein the standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS) transistor, an N-channel metal-oxide semiconductor (NMOS) transistor, and a resistor. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1, wherein the plurality of metal rails includes: a first metal rail, the first metal rail being part of the power grid and embedded in a deep trench inside the substrate; a second metal rail, the second metal rail being part of the power grid and embedded in a shallow trench above the first metal rail; and at least one via between the first metal rail and the second metal rail in the power grid. ### Claim 14 (depends on 1) The semiconductor device as claimed in claim 1, wherein the plurality of metal rails includes: a first metal rail, the first metal rail being part of the power grid and embedded in a deep trench inside the substrate; a second metal rail, the second metal rail being part of the power grid and embedded in a shallow trench above the first metal rail; and a high-k dielectric part between the first metal rail and the second metal rail in the power grid. ### Claim 15 A semiconductor device, comprising: a substrate; at least one Power Distribution Network (PDN) layer embedded within the substrate, the at least one PDN layer being a single layer and including a power line, a ground line, and a high-k dielectric part between the power line and the ground line; and a standard cell embedded within the substrate, the standard cell disposed on and overlapping a portion of the at least one PDN layer in a direction perpendicular to a top surface of the substrate, wherein the power line, the ground line, the high-k dielectric part, and the portions of the at least one PDN layer are embedded within the substrate to be surrounded by material of the substrate. ### Claim 16 (depends on 15) The semiconductor device as claimed in claim 15, further comprising back-end-of-line layers on the substrate. ### Claim 17 (depends on 15) The semiconductor device as claimed in claim 15, wherein the standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS) transistor, an N-channel metal-oxide semiconductor (NMOS) transistor, and a resistor. ### Claim 18 A semiconductor device, comprising: a substrate; at least one top Power Distribution Network (PDN) layer embedded within the substrate, the at least one top PDN layer including a first power line, a first ground line, and a first high-k dielectric part between the first power line and the first ground line; at least one bottom PDN layer embedded within the substrate, the at least one bottom PDN layer including a second power line, a second ground line, and a second high-k dielectric part between the second power line and the second ground line; and at least one standard cell embedded within the substrate, the at least one standard cell disposed on and overlapping a portion of the at least one top PDN layer in a direction perpendicular to a top surface of the substrate, wherein the first and second power lines, the first and second ground lines, and the portions of the at least one top PDN layer are embedded within the substrate to be surrounded by material of the substrate. ### Claim 19 (depends on 18) The semiconductor device as claimed in claim 18, further comprising back-end-of-line layers on the substrate. ### Claim 20 (depends on 18) The semiconductor device as claimed in claim 18, wherein the at least one standard cell includes at least one of a diode, a P-channel metal-oxide semiconductor (PMOS) transistor, an N-channel metal-oxide semiconductor (NMOS) transistor, and a resistor.