# US 12,772,847 B2 · Cooling for back side power distribution network > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,847 B2 - Document ID: US12772847B2 - Status: Granted - Kind: B2 - Application number: 18/541,669 - Filed: 2023-12-15 - Published: 2025-06-19 - Granted: 2026-10-20 - Earliest claimed: 2023-12-15 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Qianwen Chen; Joshua M. Rubin; Ruilong Xie; Tao Li - Web page: https://patentgrep.com/patent/US12772847B2 ## CPC - H10W 40/47: by flowing liquids, e.g. forced water cooling - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electrical device that includes thermal cooling through silicon vias (TSVs) and micro-channels embedded in the carrier wafer for back side power distribution networks (BSPDN). The carrier wafer is at one end of a stacked structure providing the electrical device. At least one active device layer in the stacked structure that is present a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSVs) and micro-channels. ## Claims ### Claim 1 An electrical device comprising: a first die level including first thermal cooling through silicon vias (TSV) in contact with fluidic channels; and a second die level including second thermal cooling TSV and electrical connection TSV, wherein at least one active device layer is in a level of the electrical device that is separate from a level containing the first thermal cooling TSV, the second thermal cooling TSV and the electrical connection TSV. ### Claim 2 (depends on 1) The electrical device of claim 1, wherein the first die level includes a first silicon containing layer having the first thermal cooling TSV embedded therein. ### Claim 3 (depends on 2) The electrical device of claim 2, wherein the first die level includes metal wiring in a first back end of the line (BEOL) level that is in contact with the first thermal cooling TSV that are embedded in the first silicon containing layer. ### Claim 4 (depends on 3) The electrical device of claim 3, wherein the first BEOL level is positioned between a first active device layer of the at least one active device layer and the first silicon containing layer having the first thermal cooling TSV present therein. ### Claim 5 (depends on 4) The electrical device of claim 4, wherein the first active device layer is present on a first back side interconnect. ### Claim 6 (depends on 1) The electrical device of claim 1, wherein the first die level and the second die level are separated by a fluidic channel level, wherein the electrical connection TSV extend through the fluidic channel level to transmit electrical current between the first and second die level. ### Claim 7 (depends on 1) The electrical device of claim 1, wherein the second die level includes a second silicon containing layer having the second thermal cooling TSV and the electrical connection TSV embedded therein. ### Claim 8 (depends on 7) The electrical device of claim 7, wherein the second die level includes a second active device layer. ### Claim 9 (depends on 8) The electrical device of claim 8, wherein the second active device layer is separated from the second silicon containing layer by a second back end of the line (BEOL) level, the second thermal cooling TSV and the electrical connection TSV extending into the second BEOL level. ### Claim 10 (depends on 8) The electrical device of claim 8, wherein the second active device layer is present on a second back side interconnect. ### Claim 11 An electrical device comprising: a fluidic channel level including thermal cooling through silicon vias (TSV) embedded through a silicon-containing layer, wherein a cap layer for the fluidic channel level includes an opening therethrough to channels containing the thermal cooling TSV; and at least one active device layer is in a level of the electrical device that is separate from a level containing the thermal cooling TSV. ### Claim 12 (depends on 11) The electrical device of claim 11, further comprising a back end of the line (BEOL) level that is in contact with the thermal cooling TSV that are embedded in the silicon-containing layer. ### Claim 13 (depends on 12) The electrical device of claim 12, wherein the BEOL level is positioned between the at least one active device layer and the silicon-containing layer having the thermal cooling TSV present therein. ### Claim 14 (depends on 13) The electrical device of claim 13, wherein the at least one active device layer is present on a back side interconnect. ### Claim 15 An electrical device comprising: thermal cooling through silicon vias (TSV) embedded through a silicon-containing layer and in contact with fluidic channels, wherein the silicon-containing layer is at one end of a stacked structure providing the electrical device; and at least one active device layer in the stacked structure that is present in a level of the electrical device that is separate from a level containing the thermal cooling TSV. ### Claim 16 (depends on 15) The electrical device of claim 15, wherein the thermal cooling TSV have a face that is coplanar with a face of the silicon-containing layer. ### Claim 17 (depends on 15) The electrical device of claim 15, wherein the thermal cooling TSV have a face that protrudes beyond a face of the silicon-containing layer. ### Claim 18 (depends on 15) The electrical device of claim 15, further comprising a back end of the line (BEOL) level that is in contact with the thermal cooling TSV that are embedded in the silicon containing silicon-containing layer, wherein the BEOL level is positioned between the at least one active device layer and the silicon-containing layer having the thermal cooling TSV present therein. ### Claim 19 (depends on 18) The electrical device of claim 18, wherein the at least one active device layer is present on a back side interconnect. ### Claim 20 (depends on 15) The electrical device of claim 15, wherein the stacked structure does not include well isolation for the fluidic channels.