# US 12,772,816 B2 · Self-aligned backside contact in nanosheet without BDI

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- Number: US 12,772,816 B2
- Document ID: US12772816B2
- Status: Granted
- Kind: B2
- Application number: 17/945,418
- Filed: 2022-09-15
- Published: 2024-03-21
- Granted: 2026-10-20
- Earliest claimed: 2022-09-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chen Zhang; Ruilong Xie; Julien Frougier; Heng Wu; Min Gyu Sung
- Web page: https://patentgrep.com/patent/US12772816B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/0698: {Local interconnections}
- H10W 20/427: {Power or ground buses}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer and a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below via spacers of the nanosheet transistor. The backside contact is closer to a backside of the wafer than a frontside of the wafer. The dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.

## Claims

### Claim 1

A semiconductor structure comprising:
a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer; and
a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below via spacers of the nanosheet transistor.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the backside contact is closer to a backside of the wafer than a frontside of the wafer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the backside contact directly contacts a top surface of a source/drain (S/D) epi region.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the dielectric liner directly contacts the S/D epi region.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner has a generally L-shaped configuration.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner is vertically aligned with the via spacers.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner is vertically aligned with inner spacers of a nano sheet stack of the nanosheet transistor.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric liner is thinner than the via spacers.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the via spacers and the dielectric liner collectively encompass the backside contact.

### Claim 10

A semiconductor structure comprising:
a backside contact of a nanosheet transistor extending to a top surface of a source/drain (S/D) epi region; and
a dielectric liner disposed directly between the backside contact and a silicon (Si) layer of a wafer and in direct contact with the backside contact.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric liner is located below via spacers of the nanosheet transistor.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the dielectric liner is vertically aligned with the via spacers.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, wherein the dielectric liner is thinner than the via spacers.

### Claim 14 (depends on 10)

The semiconductor structure of claim 10, wherein the backside contact is located on the Si layer.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein the backside contact is closer to a backside of the wafer than a frontside of the wafer.

### Claim 16 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric liner has a generally L-shaped configuration.

### Claim 17 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.

### Claim 18

A method comprising:
positioning a backside contact of a nanosheet transistor on a silicon (Si) layer of a wafer; and
disposing a dielectric liner between the backside contact and the Si layer such that the dielectric liner is located below via spacers of the nanosheet transistor.

### Claim 19 (depends on 18)

The method of claim 18, wherein the backside contact is closer to a backside of the wafer than a frontside of the wafer.

### Claim 20 (depends on 18)

The method of claim 18, wherein the dielectric liner is vertically aligned with the via spacers.