# US 12,772,589 B2 · Dielectric structure for small pixel designs

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- Number: US 12,772,589 B2
- Document ID: US12772589B2
- Status: Granted
- Kind: B2
- Application number: 18/149,767
- Filed: 2023-01-04
- Published: 2024-01-18
- Granted: 2026-10-20
- Earliest claimed: 2022-07-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei Long Chen; Wen-I Hsu; Feng-Chi Hung; Jen-Cheng Liu; Dun-Nian Yaung
- Web page: https://patentgrep.com/patent/US12772589B2

## CPC

- H10F 39/807: {Pixel isolation structures}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/811: {Interconnections}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprise a substrate having a first region and a second region. A first gate overlies the first region. A second gate overlies the second region. A deep trench isolation (DTI) structure is in the substrate and laterally between the first region and the second region. A first floating diffusion node is in the first region. A second floating diffusion node is in the second region. An interlayer dielectric (ILD) structure is over the substrate. A dielectric structure is between the ILD structure and the substrate. The dielectric structure is laterally between the first and second floating diffusion nodes. The dielectric structure is laterally spaced from the first and second gates. The dielectric structure overlies the DTI structure. A width of the dielectric structure is greater than a width of the DTI structure.

## Claims

### Claim 1

A method for forming an image sensor, the method comprising:
forming a first photodetector and a second photodetector bordering each other in a semiconductor substrate;
forming a first transfer gate along a first side of the semiconductor substrate, wherein the semiconductor substrate has a second side opposite the first side;
forming a second transfer gate along the first side of the semiconductor substrate;
forming a dielectric structure along the first side of the semiconductor substrate and laterally between the first transfer gate and the second transfer gate, wherein the dielectric structure has a cross-shaped top geometry at a boundary between the first and second photodetectors;
after the dielectric structure is formed, forming a first floating diffusion node in the semiconductor substrate and laterally between the first transfer gate and the dielectric structure;
after the dielectric structure is formed, forming a second floating diffusion node in the semiconductor substrate and laterally between the second transfer gate and the dielectric structure;
forming an etch stop layer over the first transfer gate, the second transfer gate, the dielectric structure, the first side of the semiconductor substrate, the first floating diffusion node, and the second floating diffusion node;
forming an interlayer dielectric (ILD) structure over the etch stop layer;
forming a trench in the semiconductor substrate, wherein the trench is formed laterally between the first floating diffusion node and the second floating diffusion node, wherein the trench is formed extending fully through the semiconductor substrate from the first side of the semiconductor substrate to the second side of the semiconductor substrate, and wherein the trench is formed with a portion of the trench disposed laterally within a perimeter of the dielectric structure; and
forming a deep trench isolation (DTI) structure in the semiconductor substrate, wherein forming the DTI structure comprises depositing a dielectric material in the trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the dielectric structure comprises:
before the etch stop layer is formed, depositing a dielectric layer over the first side of the semiconductor substrate, the first transfer gate, and the second transfer gate;
forming a patterned masking layer on the dielectric layer; and
with the patterned masking layer on the dielectric layer, performing an etching process on the dielectric layer to etch the dielectric layer according to the patterned masking layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a first sidewall spacer over the first side of the semiconductor substrate and along sidewalls of the first transfer gate; and
forming a second sidewall spacer over the first side of the semiconductor substrate and along sidewalls of the second transfer gate, wherein forming the first sidewall spacer and the second sidewall spacer comprises the etching process removing horizontal portions of the dielectric layer, thereby leaving vertical portions of the dielectric layer in place as the first sidewall spacer and the second sidewall spacer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the DTI structure has a distal end contacting the dielectric structure and spaced from the first floating diffusion node and the second floating diffusion node.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
doping the semiconductor substrate to form a p-well straddling a first photosensitive region of the semiconductor substrate and a second photosensitive region of the semiconductor substrate, wherein the dielectric structure contacts both the p-well and the DTI structure after forming the DTI structure.

### Claim 6

A method for forming an image sensor, the method comprising:
forming a pair of photodetectors bordering in a semiconductor substrate;
forming a pair of gate electrodes respectively overlying the pair of photodetectors;
depositing a dielectric layer overlying the pair of gate electrodes and a boundary region between the pair of gate electrodes;
forming a mask overlying the boundary region, between and laterally offset from the pair of gate electrodes;
performing an etch into the dielectric layer with the mask in place to form a dielectric structure underlying the mask at the boundary region and to further form a pair of sidewall spacers respectively on sidewalls of the pair of gate electrodes;
doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes and outside the boundary region; and
forming a trench isolation structure extending completely through the semiconductor substrate at the boundary region;
wherein the dielectric layer extends along individual top surfaces of the pair of gate electrodes and the sidewalls of the pair of gate electrodes, wherein the etch clears the dielectric layer from the individual top surfaces of the pair of gate electrodes to expose the individual top surfaces of the pair of gate electrodes and concurrently forms the dielectric structure and the pair of sidewall spacers, and wherein the etch further forms the pair of sidewall spacers with a height greater than a height of the dielectric structure and from portions of the dielectric layer having individual top surfaces exposed at completion of the etch.

### Claim 7 (depends on 6)

The method of claim 6, wherein the trench isolation structure contacts the dielectric structure.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
depositing an etch stop layer overlying the pair of gate electrodes, the pair of sidewall spacers, and the dielectric structure; and
forming a pair of contacts extending through the etch stop layer respectively to the pair of floating diffusion nodes.

### Claim 9 (depends on 6)

The method of claim 6, wherein the forming of the trench isolation structure comprises:
performing an additional etch into the semiconductor substrate from an opposite side of the semiconductor substrate as the pair of gate electrodes, wherein the additional etch forms a trench exposing the dielectric structure and spaced from the pair of floating diffusion nodes.

### Claim 10 (depends on 6)

The method of claim 6, wherein the dielectric structure blocks dopants from entering the semiconductor substrate at the boundary region during the doping.

### Claim 11 (depends on 6)

The method according to claim 6, wherein the dielectric layer contacts the individual top surfaces of the pair of gate electrodes and the sidewalls of the pair of gate electrodes.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the dielectric layer, the dielectric structure, and the pair of sidewall spacers have only one material composition.

### Claim 13

A method for forming an image sensor, the method comprising:
forming a pair of photodetectors bordering in a semiconductor substrate;
doping the semiconductor substrate to form a well region spaced from the pair of photodetectors;
forming a pair of gate electrodes respectively overlying the pair of photodetectors and respectively on opposite sides of the well region;
depositing a dielectric layer overlying the pair of gate electrodes and the well region;
patterning the dielectric layer to form a dielectric structure between and spaced from the pair of gate electrodes;
doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes in the well region and separated from each other by a portion of the well region masked by the dielectric structure; and
forming a pair of contact vias extending respectively to the pair of floating diffusion nodes with the dielectric structure in place, wherein the pair of contact vias are formed spaced from the dielectric structure, which is entirely formed before the pair of floating diffusion nodes are formed.

### Claim 14 (depends on 13)

The method of claim 13, wherein the pair of floating diffusion nodes have a doping type opposite a doping type of the well region.

### Claim 15 (depends on 13)

The method of claim 13, wherein the dielectric structure comprises silicon nitride.

### Claim 16 (depends on 13)

The method according to claim 13, wherein the dielectric structure has a cross-shaped top geometry at a boundary between the pair of photodetectors.

### Claim 17 (depends on 13)

The method according to claim 13, further comprising:
depositing an etch stop layer overlying the pair of gate electrodes and the dielectric structure after the doping and before the forming of the pair of contact vias, wherein the etch stop layer extends to the pair of floating diffusion nodes and contacts individual top surfaces of the pair of gate electrodes.

### Claim 18 (depends on 13)

The method according to claim 13, wherein the dielectric structure has a top geometry with a first lateral recess and a second lateral recess in which the pair of contact vias are respectively arranged.

### Claim 19 (depends on 13)

The method according to claim 13, further comprising:
forming four photodetectors, including the pair of photodetectors, arranged in two rows and two columns to form a two-by-two photodetector group, wherein, in a plan view, the four photodetectors have individual inner corners at a center of the two-by-two photodetector group, and wherein, in the plan view, the dielectric structure has a lateral recess at each of the individual inner corners of the four photodetectors and is laterally offset from remaining corners of the four photodetectors.

### Claim 20 (depends on 19)

The method according to claim 19, wherein, in the plan view, the dielectric structure is spaced from an outer perimeter of the two-by-two photodetector group.