# US 12,772,567 B2 · Metal insulator metal capacitor between two stacked transistors separated by an insulator

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- Number: US 12,772,567 B2
- Document ID: US12772567B2
- Status: Granted
- Kind: B2
- Application number: 18/466,871
- Filed: 2023-09-14
- Published: 2025-03-20
- Granted: 2026-10-20
- Earliest claimed: 2023-09-14
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Huimei Zhou; Shahrukh Khan; Baozhen Li; Ruilong Xie; Yoo-Mi Lee; Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US12772567B2

## CPC

- H10D 86/80: characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10D 86/01: Manufacture or treatment
- H10D 86/0214: {using temporary substrates}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including a first stacked nanosheet Field Effect Transistor (FET), a second stacked nanosheet, a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet and an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet. An embodiment where the first stacked nanosheet and the second stacked nanosheet each include an upper stacked nanosheet and a lower stacked nanosheet, the upper stacked nanosheet and the lower stacked nanosheet each include alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another. Forming a first stacked nanosheet, forming a second stacked nanosheet, forming a MIM capacitor between the first stacked nanosheet and the second stacked nanosheet and forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.

## Claims

### Claim 1

A semiconductor device comprising:
a first stacked nanosheet transistor adjacent to a second stacked nanosheet transistor;
a metal-insulator-metal capacitor between the first stacked nanosheet transistor and the second stacked nanosheet transistor; and
an insulator layer separating the metal-insulator-metal capacitor from each of the first stacked nanosheet transistor and the second stacked nanosheet transistor.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a contact below the second stacked nanosheet transistor connecting a first electrode of the metal-insulator-metal capacitor and a lower source drain of the second stacked nanosheet transistor.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a contact above the metal-insulator-metal capacitor and in electrical contact with an inner plate of the metal-insulator-metal capacitor.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the insulator layer directly contacts both first channels of the first stacked nanosheet transistor and second channels of the second stacked nanosheet transistor.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the metal-insulator-metal capacitor comprises an outer plate and an inner plate separated by an insulator layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a topmost surface of the insulator layer is above a topmost surface of the metal-insulator-metal capacitor.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a topmost surface of the metal-insulator-metal capacitor is below a topmost surface of a first gate of the first stacked nanosheet transistor.

### Claim 8

A semiconductor device comprising:
a first stacked nanosheet transistor comprising a first upper transistor and a first lower transistor separated by a middle dielectric isolation layer;
a second stacked nanosheet transistor comprising a second upper transistor and a second lower transistor separated by the middle dielectric isolation layer;
a metal-insulator-metal capacitor between the first stacked nanosheet transistor and the second stacked nanosheet transistor; and
an insulator layer separating the metal-insulator-metal capacitor from each of the first stacked nanosheet transistor and the second stacked nanosheet transistor.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising:
a contact below the second stacked nanosheet transistor connecting a first electrode of the metal-insulator-metal capacitor and a lower source drain of the second stacked nanosheet transistor.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, further comprising:
a contact above the metal-insulator-metal capacitor and in electrical contact with an inner plate of the metal-insulator-metal capacitor.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein the insulator layer directly contacts both first channels of the first stacked nanosheet transistor and second channels of the second stacked nanosheet transistor.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8, wherein the metal-insulator-metal capacitor comprises an outer plate and an inner plate separated by an insulator layer.

### Claim 13 (depends on 8)

The semiconductor device according to claim 8, wherein a topmost surface of the insulator layer is above a topmost surface of the metal-insulator-metal capacitor.

### Claim 14 (depends on 8)

The semiconductor device according to claim 8, wherein a topmost surface of the metal-insulator-metal capacitor is below a topmost surface of a first gate of the first stacked nanosheet transistor.

### Claim 15

A method comprising:
forming a first stacked nanosheet transistor adjacent to a second stacked nanosheet transistor;
forming a metal-insulator-metal capacitor between the first stacked nanosheet transistor and the second stacked nanosheet transistor; and
forming an insulator layer separating the metal-insulator-metal capacitor from each of the first stacked nanosheet transistor and the second stacked nanosheet transistor.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising:
forming a contact below the second stacked nanosheet transistor connecting a first electrode of the metal-insulator-metal capacitor and a lower source drain of the second stacked nanosheet transistor.

### Claim 17 (depends on 15)

The method according to claim 15, further comprising:
forming a contact above the metal-insulator-metal capacitor and in electrical contact with an inner plate of the metal-insulator-metal capacitor.

### Claim 18 (depends on 15)

The method according to claim 15, wherein the insulator layer directly contacts both first channels of the first stacked nanosheet transistor and second channels of the second stacked nanosheet transistor.

### Claim 19 (depends on 15)

The method according to claim 15, wherein a topmost surface of the insulator layer is above a topmost surface of the metal-insulator-metal capacitor.

### Claim 20 (depends on 15)

The method according to claim 15, wherein a topmost surface of the metal-insulator-metal capacitor is below a topmost surface of a first gate of the first stacked nanosheet transistor.