# US 12,772,558 B2 · Domain merger cell to abut power domains for chip area reduction

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- Number: US 12,772,558 B2
- Document ID: US12772558B2
- Status: Granted
- Kind: B2
- Application number: 18/454,376
- Filed: 2023-08-23
- Published: 2025-02-27
- Granted: 2026-10-20
- Earliest claimed: 2023-08-23
- Assignees: QUALCOMM Incorproated
- Applicants: QUALCOMM Incorporated
- Inventors: Kamesh Medisetti; Sharad Kumar Gupta; Sudesh Chandra Srivastava; Somesh Agarwal; Udayakiran Kumar Yallamaraju; Anand Ashok Baligatti; Girish T P; Ankur Mehrotra; Gousulu Kandukuru; Abhinav Chauhan; Amit Kashyap; Parissa Najdesamii
- Web page: https://patentgrep.com/patent/US12772558B2

## CPC

- H10D 84/907: {CMOS gate arrays}
- H10D 84/981: {Power supply lines}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A chip includes a merger cell including a first p-type length of diffusion (LOD) region extending in a first direction, a first n-well underneath the first p-type LOD region, a first supply rail configured to receive a first supply voltage, and a first n-tap coupling the first n-well to the first supply rail. The merger cell also includes a second p-type length of diffusion (LOD) region extending in the first direction, a second n-well underneath the second p-type LOD region, a second supply rail configured to receive a second supply voltage different from the first supply voltage, and a second n-tap coupling the second n-well to the second supply rail.

## Claims

### Claim 1

A chip, comprising:
a merger cell, wherein the merger cell comprises:
a first p-type length of diffusion (LOD) region extending in a first direction;
a first n-well underneath the first p-type LOD region;
a first supply rail configured to receive a first supply voltage;
a first n-tap coupling the first n-well to the first supply rail;
a second p-type length of diffusion (LOD) region extending in the first direction;
a second n-well underneath the second p-type LOD region;
a second supply rail configured to receive a second supply voltage different from the first supply voltage; and
a second n-tap coupling the second n-well to the second supply rail.

### Claim 2 (depends on 1)

The chip of claim 1, wherein the first supply rail and the second supply rail are aligned in a second direction that is perpendicular to the first direction, and the second supply rail is separated from the first supply rail in the first direction.

### Claim 3 (depends on 2)

The chip of claim 2, wherein the first supply rail and the second supply rail are formed from a same metal layer.

### Claim 4 (depends on 1)

The chip of claim 1, wherein the first p-type LOD region comprises:
a first oxide diffusion (OD) region extending in the first direction; and
first gates formed over the first OD region, wherein the first gates are coupled to the first supply rail.

### Claim 5 (depends on 4)

The chip of claim 4, wherein the second p-type LOD region comprises:
a second OD region extending in the first direction; and
second gates formed over the second OD region, wherein the second gates are coupled to the second supply rail.

### Claim 6 (depends on 5)

The chip of claim 5, wherein each of the first OD region and the second OD region is P+ doped.

### Claim 7 (depends on 5)

The chip of claim 5, wherein:
the first n-tap comprises a third OD region extending in the first direction, wherein the third OD region is coupled to the first supply rail and the first n-well, and the third OD region is separated from the first OD region in the first direction; and
the second n-tap comprises a fourth OD region extending in the first direction, wherein the third OD region is coupled to the second supply rail and the second n-well, and the fourth OD region is separated from the second OD region in the first direction.

### Claim 8 (depends on 7)

The chip of claim 7, wherein:
each of the first OD region and the second OD region is P+ doped; and
each of the third OD region and the fourth OD region is N+ doped.

### Claim 9 (depends on 1)

The chip of claim 1, wherein the merger cell further comprises:
a first n-type LOD region extending in the first direction; and
a second n-type LOD region extending in the first direction.

### Claim 10 (depends on 9)

The chip of claim 9, wherein the merger cell further comprises a ground rail, and the first n-type LOD region comprises:
a first oxide diffusion (OD) region extending in the first direction; and
first gates formed over the first OD region, wherein the first gates are coupled to the ground rail.

### Claim 11 (depends on 10)

The chip of claim 10, wherein the second n-type LOD region comprises:
a second OD region extending in the first direction; and
second gates formed over the second OD region, wherein the second gates are coupled to the ground rail.

### Claim 12 (depends on 11)

The chip of claim 11, wherein the ground rail is contiguous across the merger cell in the first direction.

### Claim 13 (depends on 11)

The chip of claim 11, wherein the first supply rail, the second supply rail, and the ground rail are formed from a same metal layer.

### Claim 14 (depends on 11)

The chip of claim 11, wherein each of the first OD region and the second OD region is N+ doped.

### Claim 15 (depends on 11)

The chip of claim 11, wherein the merger cell further comprises:
a first p-tap coupled to the ground rail; and
a second p-tap coupled to the ground rail.

### Claim 16 (depends on 11)

The chip of claim 11, wherein the first p-type LOD region comprises:
a third region extending in the first direction; and
third gates formed over the third OD region, wherein the third gates are coupled to the first supply rail.

### Claim 17 (depends on 16)

The chip of claim 16, wherein the second p-type LOD region comprises:
a fourth OD region extending in the first direction; and
fourth gates formed over the fourth OD region, wherein the fourth gates are coupled to the second supply rail.

### Claim 18 (depends on 17)

The chip of claim 17, wherein:
each of the first OD and the second OD is N+ doped; and
each of the third OD and the fourth OD is P+ doped.

### Claim 19 (depends on 1)

The chip of claim 1, further comprising:
a first cell in a first voltage domain abutting a first side of the merger cell; and
a second cell in a second voltage domain abutting a second side of the merger cell.

### Claim 20 (depends on 19)

The chip of claim 19, wherein the first side and the second side are opposite sides of the merger cell.