# US 12,772,539 B2 · Integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,539 B2 - Document ID: US12772539B2 - Status: Granted - Kind: B2 - Application number: 18/471,260 - Filed: 2023-09-20 - Published: 2024-08-01 - Granted: 2026-10-20 - Earliest claimed: 2023-01-31 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chaeho Na; Sangkoo Kang; Donghyun Roh; Dahye Kim - Web page: https://patentgrep.com/patent/US12772539B2 ## CPC - H10D 64/671: {the conductor having lateral variation in doping or structure} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/6729: {characterised by the electrodes} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 64/01: Manufacture or treatment - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit device includes a gate line disposed on a fin-type active region, a source/drain region disposed on the fin-type active region, and an insulating spacer structure that covers the gate line and the source/drain region. The insulating spacer structure includes a first spacer portion that covers the sidewall of the gate line, a second spacer portion integrally connected to the first spacer portion, where the second spacer portion protrudes in a first lateral direction and covers a partial region of a sidewall of the source/drain region, and a spacer corner portion that fills a corner space defined by the gate line and the source/drain region between the first spacer portion and the second spacer portion. The insulating spacer structure has a single film structure that includes a SiOC film doped with about 0 at % to about 5 at % of nitrogen atoms. ## Claims ### Claim 1 An integrated circuit device, comprising: a fin-type active region that extends along a first lateral direction on a substrate; a pair of gate lines that extend along a second lateral direction on the fin-type active region, wherein the second lateral direction intersects the first lateral direction; a source/drain region disposed on the fin-type active region and interposed between the pair of gate lines; and a pair of insulating spacer structures that cover the pair of gate lines and the source/drain region, wherein each insulating spacer structure of the pair of insulating spacer structures comprises: a first spacer portion that covers a sidewall of one gate line of the pair of gate lines, wherein the first spacer portion extends along the second lateral direction; a second spacer portion integrally connected to the first spacer portion, wherein the second spacer portion protrudes in the first lateral direction and covers a partial region of a sidewall of the source/drain region; and a spacer corner portion that fills corner spaces defined by the one gate line and the source/drain region between the first spacer portion and the second spacer portion, wherein each insulating spacer structure of the pair of insulating spacer structures has a single film structure that includes a silicon oxycarbide (SiOC) film doped with about 0 at % to about 5 at % of nitrogen atoms, and wherein, in each insulating spacer structure of the pair of insulating spacer structures, the second spacer portion has a planar shape of which a width in the second lateral direction that gradually decreases with increasing distance in the first lateral direction from the one gate line. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the source/drain region includes a first portion that has a greatest width in the second lateral direction, and the first portion comprises facet-free sidewall portions on both sides in the second lateral direction, wherein each facet-free sidewall portion extends in a vertical direction, and the first portion of the source/drain region does not overlap the insulating spacer structure in the vertical direction. ### Claim 3 (depends on 1) The integrated circuit device of claim 1, wherein each of a thickness of the spacer corner portion in the first lateral direction and a thickness of the spacer corner portion in the second lateral direction is greater than a thickness of the first spacer portion in the first lateral direction. ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein the second spacer portions included in the pair of insulating spacer structures are integrally connected to each other. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein each of the sidewalls of the source/drain region in the second lateral direction includes at least one crystal facet and a facet-free sidewall portion, and a height of the facet-free sidewall portion in a vertical direction is greater than a height of the at least one crystal facet in a vertical direction. ### Claim 6 (depends on 1) The integrated circuit device of claim 1, wherein each of the sidewalls of the source/drain region in the second lateral direction includes a first crystal facet that includes a surface inclined in a direction toward the substrate, a second crystal facet that includes a surface inclined in a direction away from the substrate, and a facet-free sidewall portion that extends in a vertical direction, and the first crystal facet and the second crystal facet are spaced apart from each other in the vertical direction with the facet-free sidewall portion interposed therebetween. ### Claim 7 (depends on 1) The integrated circuit device of claim 1, wherein each insulating spacer structure of the pair of insulating spacer structures includes a SiOC film that does not include nitrogen atoms. ### Claim 8 (depends on 1) The integrated circuit device of claim 1, wherein the pair of insulating spacer structures includes about 2 at % to about 40 at % of carbon atoms, about 30 at % to about 60 at % of silicon atoms, and about 40 at % to about 70 at % of oxygen atoms. ### Claim 9 (depends on 1) The integrated circuit device of claim 1, further comprising a device isolation film that covers both sidewalls of the fin-type active region, wherein a lowermost surface of the source/drain region is coplanar with an uppermost surface of the device isolation film. ### Claim 10 (depends on 1) The integrated circuit device of claim 1, further comprising: a device isolation film that covers both sidewalls of the fin-type active region; and an insulating liner that covers the source/drain region and the device isolation film, wherein the fin-type active region includes a recess that has a lowermost surface at a vertical level lower than a vertical level of a fin top surface of the fin-type active region, the source/drain region includes a crystal facet that includes a surface inclined toward the substrate from the lowermost surface of the recess, and the insulating liner is in contact with the fin-type active region, the source/drain region, and an interface between the fin-type active region and the source/drain region in a region adjacent to the lowermost surface of the recess. ### Claim 11 An integrated circuit device, comprising: a fin-type active region that extends along a first lateral direction on a substrate; at least one nanosheet that is spaced apart from a fin top surface of the fin-type active region in a vertical direction, wherein the at least one nanosheet faces the fin top surface of the fin-type active region; a gate line that surrounds the at least one nanosheet on the fin-type active region, wherein the gate line extends along a second lateral direction, wherein the second lateral direction intersects the first lateral direction; a source/drain region disposed on the fin-type active region adjacent to the gate line, wherein the source/drain region is in contact with the at least one nanosheet; an insulating spacer structure that covers a sidewall of the gate line and a portion of the source/drain region; and a device isolation film that covers both sidewalls of the fin-type active region, wherein the insulating spacer structure comprises: a first spacer portion that covers the sidewall of the gate line and extends along the second lateral direction; a second spacer portion integrally connected to the first spacer portion, wherein the second spacer portion protrudes in the first lateral direction and covers a partial region of a sidewall of the source/drain region; and a spacer corner portion that fills a corner space defined by the gate line and the source/drain region between the first spacer portion and the second spacer portion, wherein the insulating spacer structure has a single film structure that includes a silicon oxycarbide (SiOC) film doped with about 0 at % to about 5 at % of nitrogen atoms, and wherein the second spacer portion has a planar shape of which a width in the second lateral direction gradually decreases with increasing distance from the first spacer portion. ### Claim 12 (depends on 11) The integrated circuit device of claim 11, wherein the source/drain region includes a first portion that has a greatest width in the second lateral direction, wherein the first portion includes a facet-free sidewall portion that extends in the vertical direction, and a length of the facet-free sidewall portion in the vertical direction is greater than ½ of the total length of the source/drain region in the vertical direction. ### Claim 13 (depends on 11) The integrated circuit device of claim 11, wherein the source/drain region includes a first portion that has a greatest width in the second lateral direction, and the first portion includes facet-free sidewall portions on both sides in the second lateral direction, wherein each facet-free sidewall portion extends in the vertical direction, and the first portion of the source/drain region does not overlap the second spacer portion of the insulating spacer structure in the vertical direction. ### Claim 14 (depends on 11) The integrated circuit device of claim 11, wherein each of a thickness of the spacer corner portion in the first lateral direction and a thickness of the spacer corner portion in the second lateral direction is greater than a thickness of the first spacer portion in the first lateral direction. ### Claim 15 (depends on 11) The integrated circuit device of claim 11, wherein the source/drain region includes a first portion that has a greatest width in the second lateral direction, and the first portion includes facet-free sidewall portions on both sides in the second lateral direction, wherein each facet-free sidewall portion extends in the vertical direction, and the first portion of the source/drain region overlaps the second spacer portion of the insulating spacer structure in the vertical direction. ### Claim 16 (depends on 11) The integrated circuit device of claim 11, wherein each of the sidewalls of the source/drain region in the second lateral direction includes a first crystal facet, a facet-free sidewall portion, and a second crystal facet that are sequentially arranged in a direction away from the fin-type active region, the first crystal facet includes a surface inclined in a direction toward the substrate, the facet-free sidewall portion includes a surface that extends in a vertical direction, and the second crystal facet includes a surface inclined in a direction away from the substrate. ### Claim 17 (depends on 11) The integrated circuit device of claim 11, wherein the insulating spacer structure includes a SiOC film that does not include nitrogen atoms, wherein the SiOC film includes about 2 at % to about 40 at % of carbon atoms, about 30 at % to about 60 at % of silicon atoms, and about 40 at % to about 70 at % of oxygen atoms. ### Claim 18 An integrated circuit device, comprising: a fin-type active region; a source/drain region disposed on the fin-type active region; a pair of nanosheet stacks that are spaced apart from each other in a first lateral direction with the source/drain region interposed therebetween, wherein each nanosheet stack includes at least one nanosheet that is spaced apart in a vertical direction from a fin top surface of the fin-type active region, and each nanosheet stack faces the fin top surface of the fin-type active region and contacts the source/drain region; a pair of gate lines that each surround the at least one nanosheet of a respective nanosheet stack on the fin-type active region, wherein the pair of gate lines extend along a second lateral direction, wherein the second lateral direction intersects the first lateral direction; and a plurality of insulating spacer structures that cover the pair of gate lines and the source/drain region, wherein the plurality of insulating spacer structures include a plurality of first spacer portions, a plurality of second spacer portions, and a plurality of spacer corner portions, wherein the plurality of first spacer portions respectively cover sidewalls of the pair of gate lines, the plurality of second spacer portions are integrally connected to the plurality of first spacer portions and cover a portion of the source/drain region, and the plurality of spacer corner portions are interposed between the plurality of first spacer portions and the plurality of second spacer portions and fill corner spaces defined by the pair of gate lines and the source/drain region, wherein a thickness of each of the plurality of spacer corner portions in the first lateral direction and a thickness of each of the plurality of spacer corner portions in the second lateral direction are each greater than a thickness of each of the plurality of first spacer portions in the first lateral direction, and wherein each insulating spacer structure of the plurality of insulating spacer structures has a single film structure that includes a silicon oxycarbide (SiOC) film doped with about 0 at % to about 5 at % of nitrogen atoms.