# US 12,772,514 B2 · Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

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- Number: US 12,772,514 B2
- Document ID: US12772514B2
- Status: Granted
- Kind: B2
- Application number: 18/225,440
- Filed: 2023-07-24
- Published: 2023-11-16
- Granted: 2026-10-20
- Earliest claimed: 2019-01-04
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ehren Mannebach; Anh Phan; Aaron Lilak; Willy Rachmady; Gilbert Dewey; Cheng-Ying Huang; Richard Schenker; Hui Jae Yoo; Patrick Morrow
- Web page: https://patentgrep.com/patent/US12772514B2

## CPC

- H10D 62/123: {comprising junctions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires;
a first gate structure over the first vertical arrangement of nanowires; and
a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width the same as a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width greater than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the nanowires of the first vertical arrangement of nanowires have a horizontal width less than a horizontal width of the nanowires of the second vertical arrangement of nanowires.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires; and
second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires.

### Claim 6 (depends on 5)

The integrated circuit structure of claim 5, wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures.

### Claim 7 (depends on 5)

The integrated circuit structure of claim 5, wherein the first and second epitaxial source or drain structures are non-discrete first and second epitaxial source or drain structures.

### Claim 8 (depends on 5)

The integrated circuit structure of claim 5, wherein the first gate structure has dielectric sidewall spacers, and the first epitaxial source or drain structures are first embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the first gate structure, and wherein the second gate structure has dielectric sidewall spacers, and the second epitaxial source or drain structures are second embedded epitaxial source or drain structures extending beneath the dielectric sidewalls spacers of the second gate structure.

### Claim 9 (depends on 5)

The integrated circuit structure of claim 5, further comprising:
a first pair of conductive contact structures coupled to the first epitaxial source or drain structures; and
a second pair of conductive contact structures coupled to the second epitaxial source or drain structures.

### Claim 10 (depends on 1)

The integrated circuit structure of claim 1, wherein the first vertical arrangement of nanowires is over a first fin, and the second vertical arrangement of nanowires is over a second fin.

### Claim 11 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a gate endcap isolation structure between and in contact with the first gate structure and the second gate structure.

### Claim 12

An integrated circuit structure, comprising:
a vertical arrangement of nanowires, wherein all nanowires of the vertical arrangement of nanowires are oxide nanowires;
a gate stack over the vertical arrangement of nanowires, around each of the oxide nanowires, wherein the gate stack comprises a conductive gate electrode; and
an interconnect structure below the vertical arrangement of nanowires, wherein a conductive via of the interconnect structure is in contact with a bottom surface of the conductive gate electrode.

### Claim 13 (depends on 12)

The integrated circuit structure of claim 12, further comprising:
a gate contact above the vertical arrangement of nanowires, the gate contact in contact with a top surface of the conductive gate electrode,
wherein the conductive gate electrode acts as a conductive via between the gate contact and the interconnect structure.

### Claim 14 (depends on 12)

The integrated circuit structure of claim 12, wherein the oxide nanowires of the vertical arrangement of nanowires have an oxidation catalyst layer thereon.

### Claim 15

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires;
a first gate structure over the first vertical arrangement of nanowires; and
a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire.

### Claim 16 (depends on 15)

The computing device of claim 15, further comprising:
a memory coupled to the board.

### Claim 17 (depends on 15)

The computing device of claim 15, further comprising:
a communication chip coupled to the board.

### Claim 18 (depends on 15)

The computing device of claim 15, wherein the component is a packaged integrated circuit die.

### Claim 19 (depends on 15)

The computing device of claim 15, further comprising:
a battery coupled to the board.

### Claim 20 (depends on 15)

The computing device of claim 15, further comprising:
a display coupled to the board.