# US 12,772,508 B2 · CMOS fabrication methods for back-gate transistor

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- Number: US 12,772,508 B2
- Document ID: US12772508B2
- Status: Granted
- Kind: B2
- Application number: 18/364,964
- Filed: 2023-08-03
- Published: 2023-11-23
- Granted: 2026-10-20
- Earliest claimed: 2021-01-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Chieh Lu; Tzu Ang Chao; Chao-Ching Cheng; Lain-Jong Li
- Web page: https://patentgrep.com/patent/US12772508B2

## CPC

- H10D 48/362: {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/02: characterised by using material-based technologies
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 10/484: {characterised by the channel regions}
- H10K 10/84: Ohmic electrodes, e.g. source or drain electrodes
- H10K 10/88: Passivation; Containers; Encapsulations
- H10K 19/10: comprising field-effect transistors
- H10K 85/221: {Carbon nanotubes}
- H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 30/40: into insulating materials
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

## Claims

### Claim 1

A device comprising:
a dielectric isolation layer;
an n-type transistor comprising:
a first gate electrode on the dielectric isolation layer;
a first portion of a gate dielectric layer over the first gate electrode;
a first low-dimensional semiconductor layer over the first portion of the gate dielectric layer, wherein the first low-dimensional semiconductor layer comprises a metal;
first source/drain contacts on opposing sides of the first gate electrode, wherein the first source/drain contacts are in contact with first opposing portions of the first low-dimensional semiconductor layer; and
a dielectric doping layer comprising a metal oxide of a metal, wherein the metal oxide comprises aluminum oxide or hafnium oxide, and is over and contacting the first low-dimensional semiconductor layer, wherein the dielectric doping layer is in contact with the first low-dimensional semiconductor layer, and wherein the metal in the dielectric doping layer is a same metal as in the first low-dimensional semiconductor layer; and
a p-type transistor comprising:
a second gate electrode on the dielectric isolation layer;
a second portion of the gate dielectric layer over the second gate electrode;
a second low-dimensional semiconductor layer over the second portion of the gate dielectric layer;
second source/drain contacts on opposing sides of the second gate electrode, wherein the second source/drain contacts are in contact with second opposing portions of the second low-dimensional semiconductor layer; and
a dielectric passivation layer over and contacting the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doping layer are formed of different materials.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first portion and the second portion of the gate dielectric layer are portions of a continuous dielectric layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the dielectric doping layer comprises aluminum oxide, and the dielectric passivation layer comprises silicon oxide.

### Claim 4 (depends on 1)

The device of claim 1, wherein bottoms of both of the first gate electrode and the second gate electrode are in contact with a planar top surface of the dielectric isolation layer.

### Claim 5 (depends on 1)

The device of claim 1 further comprising:
a semiconductor substrate underlying the dielectric isolation layer; and
active devices comprising transistors at a top surface of the semiconductor substrate.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first source/drain contacts comprise aluminum or titanium, and the second source/drain contacts comprise palladium.

### Claim 7 (depends on 1)

The device of claim 1, wherein the first low-dimensional semiconductor layer comprises:
a higher horizontal portion overlapping the first gate electrode;
a lower horizontal portion laterally offset from the first gate electrode; and
a vertical portion connecting the higher horizontal portion to the lower horizontal portion.

### Claim 8 (depends on 1)

The device of claim 1 further comprising an interconnect structure underlying the dielectric isolation layer, wherein the interconnect structure comprises a low-k dielectric material.

### Claim 9

A device comprising:
an n-type transistor comprising:
a first gate electrode;
a first gate dielectric layer over the first gate electrode;
a first low-dimensional semiconductor layer comprising a first portion over the first gate dielectric layer, wherein the first low-dimensional semiconductor layer comprises a metal; and
a dielectric doping layer comprising a metal oxide of a metal, wherein the metal oxide comprises aluminum oxide or hafnium oxide, and is over and contacting the first low-dimensional semiconductor layer, wherein the dielectric doping layer is in contact with the first low-dimensional semiconductor layer, and wherein the metal in the dielectric doping layer is a same metal as in the first low-dimensional semiconductor layer; and
a p-type transistor comprising:
a second gate electrode;
a second gate dielectric layer over the second gate electrode;
a second low-dimensional semiconductor layer comprising a second portion over the second gate dielectric layer; and
a dielectric passivation layer over and contacting the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doping layer are formed of different materials.

### Claim 10 (depends on 9)

The device of claim 9, wherein the dielectric passivation layer comprises silicon oxide, and the dielectric doping layer comprises aluminum oxide.

### Claim 11 (depends on 9)

The device of claim 9, wherein the dielectric passivation layer comprises silicon oxide, and the dielectric doping layer comprises hafnium oxide.

### Claim 12 (depends on 11)

The device of claim 11, the hafnium oxide is hafnium-rich.

### Claim 13 (depends on 9)

The device of claim 9, wherein:
the n-type transistor comprises first source/drain contacts on opposing sides of the first gate electrode, wherein the first source/drain contacts are in contact with first opposing portions of the first low-dimensional semiconductor layer; and
the p-type transistor comprises second source/drain contacts on opposing sides of the second gate electrode, wherein the second source/drain contacts are in contact with second opposing portions of the second low-dimensional semiconductor layer, and the first source/drain contacts and the second source/drain contacts comprise different metals.

### Claim 14 (depends on 13)

The device of claim 13, wherein the first source/drain contacts comprise aluminum or titanium, and the second source/drain contacts comprise palladium.

### Claim 15 (depends on 9)

The device of claim 9, wherein the first low-dimensional semiconductor layer comprises:
a top portion directly over the first gate electrode; and
a sidewall portion on a sidewall of the first gate electrode.

### Claim 16

A device comprising:
a semiconductor substrate;
a dielectric layer over the semiconductor substrate;
an isolation layer over the dielectric layer;
a first work function layer over the isolation layer, wherein the first work function layer is an n-type work function layer;
a first low-dimensional semiconductor layer on a first top surface and a first sidewall of the first work function layer;
first source/drain contacts contacting opposing end portions of the first low-dimensional semiconductor layer; and
a dielectric doping layer over and contacting a channel portion of the first low-dimensional semiconductor layer, wherein the dielectric doping layer comprises a metal selected from aluminum and hafnium, and wherein the channel portion of the first low-dimensional semiconductor layer further comprises the metal that is comprised within the dielectric doping layer.

### Claim 17 (depends on 16)

The device of claim 16 further comprising an additional transistor formed at a surface of the semiconductor substrate, wherein the additional transistor comprises silicon or silicon germanium as a channel material.

### Claim 18 (depends on 16)

The device of claim 16 further comprising:
a second work function layer over the isolation layer, wherein the second work function layer is a p-type work function layer;
a second low-dimensional semiconductor layer on a second top surface and a second sidewall of the second work function layer;
second source/drain contacts contacting opposing end portions of the second low- dimensional semiconductor layer; and
a dielectric passivation layer, wherein the dielectric passivation layer and the second low- dimensional semiconductor layer are free from the metal.

### Claim 19 (depends on 18)

The device of claim 18, wherein the first source/drain contacts and the second source/drain contacts comprise different metals.

### Claim 20 (depends on 16)

The device of claim 16, wherein the metal comprises hafnium.