# US 12,772,437 B2 · Semiconductor device having a buffer structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,437 B2 - Document ID: US12772437B2 - Status: Granted - Kind: B2 - Application number: 17/880,723 - Filed: 2022-08-04 - Published: 2023-06-29 - Granted: 2026-10-20 - Earliest claimed: 2021-12-27 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ahrang Choi; Chansic Yoon; Hoin Ryu; Junghoon Han - Web page: https://patentgrep.com/patent/US12772437B2 ## CPC - H10B 12/34: {the transistor being at least partially in a trench in the substrate} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/48: {Data lines or contacts therefor} - H10B 12/485: {Bit line contacts} - H10W 20/092: {by smoothing the dielectric parts} - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes active regions defined by a device isolation region in a substrate; trenches extending in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the isolation region, and the buried gate structures; bit line structures extending in a second direction intersecting the first direction on the active regions and connected to the active regions; storage node contacts between the bit line structures, penetrating through the buffer structure and in contact with the active regions; and capacitor structures in contact with an upper surface of the storage node contacts. ## Claims ### Claim 1 A semiconductor device, comprising: active regions defined by a device isolation region in a substrate; trenches extending lengthwise in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the device isolation region, and the buried gate structures; bit line structures extending lengthwise in a second direction intersecting the first direction on the active regions and connected to the active regions; spacer structures that cover sidewalls of the bit line structures and are disposed on the buffer structure; storage node contacts between the bit line structures, penetrating through the buffer structure and in direct contact with the active regions; and capacitor structures in direct contact with an upper surface of the storage node contacts, wherein the buffer structure includes: a first buffer pattern extending along profiles of the upper surfaces of the active regions, the device isolation region, and the buried gate structures and having an upper surface including concave portions; a second buffer pattern including at least first portions filling the concave portions of the upper surface of the first buffer pattern, the second buffer pattern being in direct contact with the first pattern; and a third buffer pattern on the first buffer pattern and the second buffer pattern, the third buffer pattern being in direct contact with the second buffer pattern, wherein each of the bit line structures includes a first portion on an upper surface of the buffer structure and second portions penetrating through the buffer structure, wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a third direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the third direction being perpendicular to the first and second directions, wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern, wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate, wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction, wherein the spacer structures are in contact with side surfaces of the first portion of the bit line structure, and wherein the third buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the concave portions of the upper surface of the first buffer pattern are located on the buried gate structures, and wherein the first portions of the second buffer pattern vertically overlap the buried gate structures. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the buffer structure includes: a first region in which the first to third buffer patterns are stacked in sequence, and a second region in which the third buffer pattern is directly stacked on the first buffer pattern. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the first region of the buffer structure is located on the buried gate structures, and wherein the second region of the buffer structure is located on the active regions and the device isolation region. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first buffer pattern and the third buffer pattern include silicon oxide, and wherein the second buffer pattern includes silicon nitride. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second buffer pattern further includes second portions located on the first buffer pattern and connecting the first portions to each other. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein a thickness of the second portions is smaller than a thickness of the first portions. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the second portions are located on the first buffer pattern located on the upper surfaces of the active regions and the device isolation region. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein a thickness of the first buffer pattern is greater than a thickness of the third buffer pattern. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein each of the buried gate structures includes a word line in a corresponding one of the trenches and a capping pattern located on the word line. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein an uppermost surface of the third buffer pattern is at a vertical level farther away from the lower surface of the substrate than the vertical level of the uppermost portion of the upper surface of the second buffer pattern. ### Claim 12 A semiconductor device, comprising: active regions defined by a device isolation region in a substrate; buried gate structures intersecting the active regions; word lines buried in the substrate, extending lengthwise in a first direction, and located on a level lower than a level of upper surfaces of the active regions; capping patterns buried in the substrate, located on the word lines, and having upper surfaces located on a level lower than a level of the upper surfaces of the active regions; a buffer structure on the device isolation region, the active regions, and the capping patterns; bit line structures extending lengthwise in a second direction intersecting the first direction on the active regions and connected to the active regions; and spacer structures that cover sidewalls of the bit line structures and are disposed on the buffer structure, wherein each of the bit line structures includes a first portion on an upper surface of the buffer structure and second portions penetrating through the buffer structure, wherein the buffer structure includes a first region on the active regions and the device isolation region, and a second region on the capping patterns, wherein the first region has a first thickness, wherein the second region has a second thickness greater than the first thickness, wherein the buffer structure includes: a first buffer pattern extending along profiles of the upper surfaces of the active regions, the device isolation region, and the buried gate structures and having an upper surface including concave portions; a second buffer pattern including at least first portions filling the concave portions of the upper surface of the first buffer pattern; and a third buffer pattern that is on and in direct contact with the first buffer pattern, and below and in direct contact with the second buffer pattern, wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a third direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the third direction being perpendicular to the first and second directions, wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern, wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate, wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction, and wherein the second buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a lower surface of the buffer structure has a shape according to profiles of the upper surfaces of the substrate and the capping patterns. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the first region of the buffer structure includes at least a first silicon oxide layer, and wherein the second region of the buffer structure includes the first silicon oxide layer and a silicon nitride layer deposited on the first silicon oxide layer. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the buffer structure further includes a second silicon oxide layer covering the first silicon oxide layer and the silicon nitride layer in the first and second regions. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein the buffer structure includes: the first region in which the first to third buffer patterns are stacked in a sequence of the first buffer pattern, the third buff er pattern, and the second buffer pattern, and the second region in which the second buffer pattern is directly stacked on the first buffer pattern. ### Claim 17 A semiconductor device, comprising: an isolation region defining an active region within a substrate; buried gate structures intersecting the active region, extending lengthwise into the isolation region, and having upper surfaces located on a level lower than a level of an upper surface of the active region; a first buffer pattern on the buried gate structures and the isolation region, and having an upper surface including concave portions on the buried gate structures; a second buffer pattern filling the concave portions of the upper surface of the first buffer pattern and including at least first portions vertically overlapping the buried gate structures; a bit line structure on the active region and connected to the active region; and spacer structures that cover sidewalls of the bit line structure and are disposed on the second buffer pattern, wherein the bit line structure includes a first portion on an upper surface of the second buffer pattern and a second portion penetrating through the first and second buffer patterns, wherein the second buffer pattern is in direct contact with the first buffer pattern, wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a vertical direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the vertical direction being perpendicular to a horizontal upper surface of the isolation region, wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the vertical direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern, wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate, wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the vertical direction, and wherein the second buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein each of the buried gate structures includes a word line and a capping pattern on the word line, and wherein the first buffer pattern is in direct contact with the capping pattern. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein the first portions of the second buffer pattern extend in a first horizontal direction, and wherein each of first and second portions of the bit line structure extends lengthwise in a second horizontal direction intersecting the first horizontal direction. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the second buffer pattern includes: the first portions filling the concave portions of the first buffer pattern, and second portions disposed on the first buffer pattern and connecting the first portions to each other.