# US 12,772,434 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,772,434 B2 - Document ID: US12772434B2 - Status: Granted - Kind: B2 - Application number: 18/478,978 - Filed: 2023-09-29 - Published: 2024-06-13 - Granted: 2026-10-20 - Earliest claimed: 2022-12-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyeri An; Dongsik Park; Sooho Shin; Joonsuk Park; Keonhee Park; Gaeun Lee; Jihoon Chang; Yujin Cho; Hana Cho - Web page: https://patentgrep.com/patent/US12772434B2 ## CPC - H10B 12/315: {with the capacitor higher than a bit line} - H10B 12/01: {Manufacture or treatment} - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a switching element, and a data storage structure electrically connected to the switching element. The data storage structure includes first electrodes, a second electrode, and a dielectric layer between the first electrodes and the second electrode. The second electrode includes a compound semiconductor layer doped with an impurity element, the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, the two or more elements include a first element and a second element, the first element is silicon (Si), and a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %. ## Claims ### Claim 1 A semiconductor device, comprising: a switching element; and a data storage structure electrically connected to the switching element, wherein the data storage structure includes, a plurality of first electrodes; a second electrode; and a dielectric layer disposed between the plurality of first electrodes and the second electrode, wherein the second electrode includes a compound semiconductor layer doped with an impurity element, wherein the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, wherein the two or more elements include a first element and a second element, wherein the first element is silicon (Si), the second element is germanium (Ge), and the impurity element is boron (B), and wherein a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the compound semiconductor layer doped with the impurity element has a P-type conductivity. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the second electrode further includes a conductive layer on the compound semiconductor layer. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the conductive layer includes a material that differs from a material of the compound semiconductor layer. ### Claim 5 (depends on 3) The semiconductor device of claim 3, wherein the conductive layer includes titanium (Ti). ### Claim 6 (depends on 3) The semiconductor device of claim 3, further comprising a contact structure in contact with the second electrode. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the contact structure includes a barrier layer and a conductive layer on the barrier layer. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the contact structure is in contact with the conductive layer and spaced apart from the compound semiconductor layer. ### Claim 9 (depends on 6) The semiconductor device of claim 6, wherein the contact structure penetrates through the conductive layer and contacts the compound semiconductor layer. ### Claim 10 (depends on 6) The semiconductor device of claim 6, wherein the contact structure penetrates through the conductive layer and extends into the compound semiconductor layer. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising a bit line, wherein the switching element includes a gate electrode that extends in a direction that intersects the bit line, and wherein the first electrodes are located at a level higher than that of the bit line and the gate electrode. ### Claim 12 A semiconductor device, comprising: a transistor that includes a first source/drain region and a second source/drain region that are spaced apart from each other, a channel region interposed between the first and second source/drain regions, a gate dielectric layer in contact with the channel region, and a gate electrode disposed on the gate dielectric layer; a bit line electrically connected to the first source/drain region; and a data storage structure that is electrically connected to the second source/drain region, wherein the data storage structure includes, a first electrode electrically connected to the second source/drain region; a second electrode; and a dielectric layer disposed between the first electrode and the second electrode, wherein the second electrode includes a compound semiconductor layer doped with boron (B) and a conductive layer disposed on the compound semiconductor layer, wherein the compound semiconductor layer includes two or more elements, wherein the two or more elements include silicon (Si) and germanium (Ge), and wherein a concentration of the boron (B) in the compound semiconductor layer is within a range of about 0.1 at % to about 5 at %, and a concentration of the silicon (Si) in the compound semiconductor layer is within a range of about 10 at % to about 15 at %. ### Claim 13 (depends on 12) The semiconductor device of claim 12, further comprising a contact structure in contact with the second electrode, wherein the contact structure is spaced apart from the compound semiconductor layer and contacts the conductive layer. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein a thickness of the compound semiconductor layer on an upper surface of the first electrode is greater than a thickness of the conductive layer. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the first and second source/drain regions are vertically spaced apart from each other, and wherein the channel region is a vertical channel region. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein the first and second source/drain regions are spaced apart from each other in a horizontal direction and are on the same level, and wherein the channel region is a horizontal channel region. ### Claim 17 A semiconductor device, comprising: a device isolation layer that defines active regions on a substrate; gate electrodes that cross the active regions and extend into the device isolation layer; first impurity regions and second impurity regions formed in the active regions on both sides of the gate electrodes; bit lines disposed on the gate electrodes and electrically connected to the first impurity regions; upper conductive patterns disposed on side surfaces of the bit lines and electrically connected to the second impurity regions; first electrodes that vertically extend on the upper conductive patterns and are connected to the upper conductive patterns, wherein the first electrodes are horizontally spaced apart from each other; at least one supporter layer disposed between horizontally adjacent first electrodes and in contact with the first electrodes; a dielectric layer disposed on the first electrodes and the at least one supporter layer; and a second electrode disposed on the dielectric layer, wherein the second electrode includes a compound semiconductor layer doped with an impurity element and a conductive layer disposed on the compound semiconductor layer, wherein the compound semiconductor layer includes two or more elements and includes a semiconductor material doped with the impurity element, wherein the two or more elements include a first element and a second element, and wherein a concentration of the impurity element in the compound semiconductor layer is in a range of about 0.1 at % to about 5 at %, and a concentration of the first element in the compound semiconductor layer is in a range of about 10 at % to about 15 at %. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the compound semiconductor layer includes a compound semiconductor layer doped with the impurity element and that has a conductivity type, wherein the conductive layer includes titanium (Ti), the impurity element is boron (B), and the first element is silicon (Si). ### Claim 19 (depends on 17) The semiconductor device of claim 17, further comprising a contact structure in contact with the conductive layer.