# US 12,771,379 B2 · Syndrome check functionality to differentiate between error types > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,771,379 B2 - Document ID: US12771379B2 - Status: Granted - Kind: B2 - Application number: 18/804,539 - Filed: 2024-08-14 - Published: 2025-02-06 - Granted: 2026-10-20 - Earliest claimed: 2022-01-20 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Scott E. Schaefer - Web page: https://patentgrep.com/patent/US12771379B2 ## CPC - H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms} - H03M 13/43: Majority logic or threshold decoding - H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system. ## Claims ### Claim 1 A system, comprising: a host system; a memory system; and a syndrome check circuit coupled with the host system and the memory system, the syndrome check circuit operable to: receive a first signal having a first signal level and comprising a first bit, and a second signal having a second signal level and comprising a second bit, wherein a value of the first bit indicates whether the memory system detected a first error associated with first data received by the memory system and a value of the second bit indicates whether the host system detected a second error associated with the first data; and perform an error control operation on the first data based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal. ### Claim 2 (depends on 1) The system of claim 1, wherein the syndrome check circuit is further operable to: output a third signal indicating a type of error associated with the first data based at least in part on comparing the value of the first bit to the value of the second bit, and based at least in part on comparing an inverse of the level of the first signal to the level of the second signal, the level of the first signal to an inverse of the level of the second signal, and the inverse of the level of the first signal to the inverse of the level of the second signal. ### Claim 3 (depends on 2) The system of claim 2, wherein the third signal indicates that the memory system did not detect an error in the first data based at least in part on the first signal level comprising a first magnitude and that the host system did not detect an error in the first data based at least in part on the second signal level comprising a second magnitude different than the first magnitude. ### Claim 4 (depends on 2) The system of claim 2, wherein outputting the third signal further comprises: inverting the first signal, the second signal, or both, to indicate a type of the error. ### Claim 5 (depends on 1) The system of claim 1, wherein the syndrome check circuit is further operable to: detect a single-bit error at the memory system, a multi-bit error at the memory system, a single-bit error at the host system, or a multi-bit error at the host system, or any combination thereof based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal, wherein performing the error control operation is based at least in part on the detecting. ### Claim 6 (depends on 1) The system of claim 1, the syndrome check circuit further comprising: a plurality of logic gates operable to perform the error control operation on the first data. ### Claim 7 (depends on 1) The system of claim 1, further comprising: a register operable to store second data representative of one or more outputs from the syndrome check circuit. ### Claim 8 (depends on 1) The system of claim 1, wherein the first signal is received from the memory system and the second signal is received from the host system. ### Claim 9 A method, comprising: receiving, at a syndrome check circuit, a first signal having a first signal level and comprising a first bit, a value of the first bit indicating whether a memory system detected a first error associated with first data; receiving, at the syndrome check circuit, a second signal having a second signal level and comprising a second bit, a value of the second bit indicating whether a host system detected a second error associated with the first data; and performing, at the syndrome check circuit, an error control operation on the first data based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal. ### Claim 10 (depends on 9) The method of claim 9, further comprising: outputting a third signal indicating a type of error associated with the first data based at least in part on performing the error control operation on the first data, and based at least in part on comparing an inverse of the level of the first signal to the level of the second signal, the level of the first signal to an inverse of the level of the second signal, and the inverse of the level of the first signal to the inverse of the level of the second signal. ### Claim 11 (depends on 10) The method of claim 10, wherein the third signal indicates that the memory system did not detect an error in the first data based at least in part on the first signal level comprising a first magnitude and that the host system did not detect an error in the first data based at least in part on the second signal level comprising a second magnitude different than the first magnitude. ### Claim 12 (depends on 10) The method of claim 10, wherein outputting the third signal further comprises: inverting the first signal, the second signal, or both, to indicate a type of the error. ### Claim 13 (depends on 9) The method of claim 9, further comprising: detecting a single-bit error at the memory system, a multi-bit error at the memory system, a single-bit error at the host system, or a multi-bit error at the host system, or any combination thereof based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal, wherein performing the error control operation is based at least in part on the detecting. ### Claim 14 (depends on 9) The method of claim 9, wherein the first signal is received from the memory system and the second signal is received from the host system. ### Claim 15 A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: receive, at a syndrome check circuit, a first signal with a first signal level and comprising a first bit, a value of the first bit indicating whether a memory system detected a first error associated with first data; receive, at the syndrome check circuit, a second signal with a second signal level and comprising a second bit, a value of the second bit indicating whether a host system detected a second error associated with the first data; and perform, at the syndrome check circuit, an error control operation on the first data based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to: output a third signal indicating whether an error was detected in the first data based at least in part on performing the error control operation on the first data, and based at least in part on comparing an inverse of the level of the first signal to the level of the second signal, the level of the first signal to an inverse of the level of the second signal, and the inverse of the level of the first signal to the inverse of the level of the second signal. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the third signal indicates that the memory system, the host system, or both, detected an error in the first data based at least in part on the first signal level and the second signal level comprising different signal levels. ### Claim 18 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein outputting the third signal further comprises: inverting the first signal, the second signal, or both, to indicate a type of the error. ### Claim 19 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to: detect a single-bit error at the memory system, a multi-bit error at the memory system, a single-bit error at the host system, or a multi-bit error at the host system, or any combination thereof based at least in part on comparing the value of the first bit with the value of the second bit and based at least in part on comparing a level of the first signal to a level of the second signal, wherein performing the error control operation is based at least in part on the detecting. ### Claim 20 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the first signal is received from the memory system and the second signal is received from the host system.