# US 12,771,368 B2 · Bootstrapped comparator

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- Number: US 12,771,368 B2
- Document ID: US12771368B2
- Status: Granted
- Kind: B2
- Application number: 18/628,077
- Filed: 2024-04-05
- Published: 2025-10-09
- Granted: 2026-10-20
- Earliest claimed: 2024-04-05
- Assignees: Cirrus Logic, Inc.
- Applicants: Cirrus Logic International Semiconductor Ltd.
- Inventors: Rohit Bupathy Sudan; Ravi K. Kummaraguntla; Rakesh Selvaraj
- Web page: https://patentgrep.com/patent/US12771368B2

## CPC

- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/42: Sequential comparisons in series-connected stages with no change in value of analogue signal
- H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A successive approximation register analog-to-digital converter may include a reference digital-to-analog converter, a successive approximation register, and a top-plate sampled comparator configured to compare a reference signal generated by the reference digital-to-analog converter to an analog input signal in order to generate a comparator output to the successive approximation register. The top-plate sampled comparator may include sampling transistors, sampling switches, non-linear capacitors, and circuitry configured to pre-condition the comparator by maintaining a constant voltage across non-linear capacitors of the top-plate sampled comparator during a sampling phase of the comparator in order to maintain sampling linearity of the top-plate sampled comparator.

## Claims

### Claim 1

A method for maintaining sampling linearity in a top-plate sampled comparator, comprising:
pre-conditioning the comparator by maintaining a constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator, wherein the non-linear capacitors comprise parasitic capacitances of an input device of the comparator, and wherein maintaining the constant voltage comprises coupling an analog input signal of the comparator to a gate, a drain, and a source of the input device of the comparator during the sampling phase such that voltages across the parasitic capacitances of the input device are held substantially constant during the sampling phase.

### Claim 2 (depends on 1)

The method of claim 1, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises sampling an analog input signal to the comparator onto all terminals of an input device of the comparator.

### Claim 3 (depends on 1)

The method of claim 1, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling non-input terminals of an input device of the comparator to an input of the comparator.

### Claim 4 (depends on 1)

The method of claim 1, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling all terminals of an input device of the comparator to a top plate of a reference digital-to-analog converter of a successive approximation register analog-to-digital converter.

### Claim 5

A top-plate sampled comparator comprising:
sampling transistors;
sampling switches;
non-linear capacitors comprising parasitic capacitances of an input device of the comparator; and
circuitry configured to pre-condition the comparator by maintaining a constant voltage across the parasitic capacitances of the input device of the comparator during a sampling phase of the comparator in order to maintain sampling linearity of the comparator, wherein the circuitry is configured to maintain the constant voltage by coupling an analog input signal of the comparator to a gate, a drain, and a source of the input device of the comparator during the sampling phase such that voltages across the parasitic capacitances of the input device are held substantially constant during the sampling phase.

### Claim 6 (depends on 5)

The top-plate sampled comparator of claim 5, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises sampling an analog input signal to the comparator onto all terminals of an input device of the comparator.

### Claim 7 (depends on 5)

The top-plate sampled comparator of claim 5, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling non-input terminals of an input device of the comparator to an input of the comparator.

### Claim 8 (depends on 5)

The top-plate sampled comparator of claim 5, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling all terminals of an input device of the comparator to a top plate of a reference digital-to-analog converter of a successive approximation register analog-to-digital converter.

### Claim 9

A successive approximation register analog-to-digital converter comprising:
a reference digital-to-analog converter;
a successive approximation register; and
a top-plate sampled comparator configured to compare a reference signal generated by the reference digital-to-analog converter to an analog input signal in order to generate a comparator output to the successive approximation register, the comparator comprising:
sampling transistors;
sampling switches;
non-linear capacitors comprising parasitic capacitances of an input device of the comparator; and
circuitry configured to pre-condition the comparator by maintaining a constant voltage across the parasitic capacitances of the input device capacitors of the comparator during a sampling phase of the comparator in order to maintain sampling linearity of the comparator, wherein the circuitry is configured to maintain the constant voltage by coupling the analog input signal to a gate, a drain, and a source of the input device of the comparator during the sampling phase such that voltages across the parasitic capacitances of the input device are held substantially constant during the sampling phase.

### Claim 10 (depends on 9)

The successive approximation register analog-to-digital converter of claim 9, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises sampling an analog input signal to the comparator onto all terminals of an input device of the comparator.

### Claim 11 (depends on 9)

The successive approximation register analog-to-digital converter of claim 9, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling non-input terminals of an input device of the comparator to an input of the comparator.

### Claim 12 (depends on 9)

The successive approximation register analog-to-digital converter of claim 9, wherein maintaining the constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator comprises coupling all terminals of an input device of the comparator to a top plate of a reference digital-to-analog converter of a successive approximation register analog-to-digital converter.

### Claim 13 (depends on 9)

The successive approximation register analog-to-digital converter of claim 9, wherein the parasitic capacitances of the input device comprise a gate-to-source capacitance, a gate-to-drain capacitance, a drain-to-source capacitance, a source-to-bulk capacitance, and a drain-to-bulk capacitance of a sampling transistor of the comparator.

### Claim 14 (depends on 1)

The method of claim 1, wherein the parasitic capacitances of the input device comprise a gate-to-source capacitance, a gate-to-drain capacitance, and a drain-to-source capacitance of a sampling transistor of the comparator.

### Claim 15 (depends on 5)

The top-plate sampled comparator of claim 5, wherein the parasitic capacitances of the input device comprise a gate-to-source capacitance, a gate-to-drain capacitance, a drain-to-source capacitance, a source-to-bulk capacitance, and a drain-to-bulk capacitance of a sampling transistor of the comparator.