# US 12,771,330 B2 · Serial interface bus with glitch filtering > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,771,330 B2 - Document ID: US12771330B2 - Status: Granted - Kind: B2 - Application number: 18/739,820 - Filed: 2024-06-11 - Published: 2025-12-11 - Granted: 2026-10-20 - Earliest claimed: 2024-06-11 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Raymond Rosik; Zdravko Lukic; Huiqiao He; Christopher Thompson; Chris Rosolowski; John Fletcher; Edgar Marti-Arbona - Web page: https://patentgrep.com/patent/US12771330B2 ## CPC - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 5/133: using a chain of active delay devices - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A glitch filter associated with a serial interface bus may receive an input signal associated with a glitch. The glitch filter may reject the glitch based at least in part on a plurality of state machine transitions associated with the glitch filter and a set of timers associated with the glitch filter, to produce an output signal that is not associated with the glitch. The glitch filter may provide the output signal. In some aspects, the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions. The glitch filter may be implemented as an asynchronous finite state machine (AFSM) filter or a synchronous finite state machine. ## Claims ### Claim 1 A method, comprising: receiving, by a glitch filter associated with a serial interface bus, an input signal associated with a glitch; rejecting, by the glitch filter, the glitch based at least in part on a plurality of state machine transitions associated with the glitch filter and a set of timers associated with the glitch filter, wherein the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and the input signal is locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions; and providing, by the glitch filter, an output signal based at least in part on the plurality of state machine transitions and the set of timers. ### Claim 2 (depends on 1) The method of claim 1, wherein the glitch filter is a synchronous finite state machine or an asynchronous finite state machine (AFSM) digital filter. ### Claim 3 (depends on 1) The method of claim 1, wherein the glitch filter is associated with one or more delay cells and a latch, wherein an input signal level is maintained for the one or more delay cells, and the latch prevents transitions of the input signal that are narrower than a programmable bandwidth setting. ### Claim 4 (depends on 1) The method of claim 1, wherein the input signal is received from an output driver associated with the serial interface bus, wherein the output driver includes one or more switchable resistors to match an output impedance associated with the output driver with a characteristic impedance of a transmission line associated with the serial interface bus, the output driver is associated with a programmable slew rate, and the output driver is associated with an automatic slew rate control to optimize a slew rate to match the characteristic impedance of the transmission line and minimize reflections and glitches on the serial interface bus. ### Claim 5 (depends on 1) The method of claim 1, wherein the glitch is a first glitch, and further comprising: detecting, using a glitch detector associated with the serial interface bus, whether the output signal is associated with a second glitch, wherein the glitch detector is associated with a debugging of the glitch filter; and generating, at the glitch detector, an indication that the second glitch is associated with the output signal. ### Claim 6 (depends on 1) The method of claim 1, wherein the serial interface bus is associated with a power management integrated circuit (PMIC). ### Claim 7 A non-transitory computer-readable medium storing a set of instructions for filtering glitches in a serial interface bus, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to: receive, by a glitch filter associated with a serial interface bus, an input signal associated with a glitch; reject, by the glitch filter, the glitch based at least in part on a plurality of state machine transitions associated with the glitch filter and a set of timers associated with the glitch filter, wherein the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and the input signal is locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions; and provide, by the glitch filter, an output signal based at least in part on the plurality of state machine transitions and the set of timers. ### Claim 8 (depends on 7) The non-transitory computer-readable medium of claim 7, wherein the glitch filter is a synchronous finite state machine or an asynchronous finite state machine (AFSM) digital filter. ### Claim 9 (depends on 7) The non-transitory computer-readable medium of claim 7, wherein the glitch filter is associated with one or more delay cells and a latch, and the latch prevents transitions of the input signal that are narrower than a programmable bandwidth setting. ### Claim 10 (depends on 7) The non-transitory computer-readable medium of claim 7, wherein the input signal is received from an output driver associated with the serial interface bus, wherein the output driver includes one or more switchable resistors to match an output impedance associated with the output driver with a characteristic impedance of a transmission line associated with the serial interface bus. ### Claim 11 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the output driver is associated with a programmable slew rate. ### Claim 12 (depends on 10) The non-transitory computer-readable medium of claim 10, wherein the output driver is associated with an automatic slew rate control to optimize a slew rate to match the characteristic impedance of the transmission line and minimize reflections and glitches on the serial interface bus. ### Claim 13 (depends on 7) The non-transitory computer-readable medium of claim 7, wherein the input signal is a clock signal or a data signal. ### Claim 14 (depends on 7) The non-transitory computer-readable medium of claim 7, wherein the serial interface bus is associated with a power management integrated circuit (PMIC). ### Claim 15 (depends on 7) The non-transitory computer-readable medium of claim 7, further comprising instructions that, when executed, cause the device to detect, using a glitch detector associated with the serial interface bus, whether the output signal is associated with a second glitch. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, further comprising instructions that, when executed, cause the device to generate, at the glitch detector, an indication that the second glitch is associated with the output signal. ### Claim 17 An apparatus for filtering glitches in a serial interface bus, comprising: means for receiving an input signal associated with a glitch by a glitch filter; means for rejecting, by the glitch filter, the glitch based at least in part on a plurality of state machine transitions and a set of timers associated with the glitch filter, wherein the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and the input signal is locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions; and means for providing, by the glitch filter, an output signal based at least in part on the plurality of state machine transitions and the set of timers. ### Claim 18 (depends on 1) The method of claim 1, wherein the glitch filter transitions an output state only in response to an input signal edge having a pulse width that is at least a threshold duration. ### Claim 19 (depends on 1) The method of claim 1, wherein each of the high timer and the low timer is programmable. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein each of the high timer and the low timer is programmable.