# US 12,770,682 B2 · Storage device and method of performing read and write operations

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- Number: US 12,770,682 B2
- Document ID: US12770682B2
- Status: Granted
- Kind: B2
- Application number: 18/779,825
- Filed: 2024-07-22
- Published: 2026-01-22
- Granted: 2026-10-20
- Earliest claimed: 2024-07-22
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Sujit Kumar Rout; Daksheshkumar Maganbhai Malaviya; Navin Agarwal; Yattapu Viswanatha Reddy; Hemant Hemraj Parate
- Web page: https://patentgrep.com/patent/US12770682B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/418: Address circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems and methods of controlling a read operation and a write operation at a storage device storage device including: core circuitry including one or more bitcells, each bitcell accessible via a corresponding bitline and wordline; column selection circuitry to, responsive to a column select signal, select at least one bitcell via one or more bitlines; wordline selection circuitry to, responsive to a wordline select signal, select the at least one bitcell via one or more wordlines; control circuitry to, in a first mode of operation: provide a first wordline select signal to the wordline selection circuitry responsive to a first control signal; provide first and second column select signals to the column selection circuitry responsive to a second control signal, and where the first column select signal is to control a read operation and the second column select signal is to control a write operation.

## Claims

### Claim 1

A storage device comprising:
core circuitry comprising one or more bitcells, each bitcell accessible via a corresponding bitline and wordline;
column selection circuitry to, responsive to a column select signal, select at least one bitcell via one or more bitlines;
wordline selection circuitry to, responsive to a wordline select signal, select the at least one bitcell via one or more wordlines;
control circuitry to, in a first mode of operation:
provide a first wordline select signal to the wordline selection circuitry responsive to a first control signal;
provide first and second column select signals to the column selection circuitry responsive to a second control signal, and wherein:
the first column select signal is to control a read operation and the second column select signal is to control a write operation,
a transition of the second control signal triggers the read operation to complete and simultaneously triggers the write operation to begin.

### Claim 2 (depends on 1)

The storage device of claim 1, where the control circuitry is to, in a second mode of operation:
provide a second wordline select signal to the wordline selection circuitry responsive to the first control signal;
provide third and fourth column select signals to the column selection circuitry responsive to the first control signal, and where the third column select signal is to control a read operation and where the fourth column select signal is to control a write operation.

### Claim 3 (depends on 1)

The storage device of claim 1, where the first control signal comprises a first global timing signal comprising two or more pulses.

### Claim 4 (depends on 1)

The storage device of claim 1, where the second control signal is generated responsive to the first control signal.

### Claim 5 (depends on 4)

The storage device of claim 4, where the second control signal is generated responsive to a third control signal being asserted.

### Claim 6 (depends on 4)

The storage device of claim 4, where the first control signal is received at a first input of the control circuitry and where the third control signal is received at a second input of the control circuitry.

### Claim 7 (depends on 1)

The storage device of claim 1, where the write operation is to start after a pre-defined delay following the first column select signal.

### Claim 8 (depends on 1)

The storage device of claim 1, where the column selection circuitry comprises one or more column read devices and where the first column select signal is to enable a first column read device to couple a bitline to sense amplifier circuitry.

### Claim 9 (depends on 1)

The storage device of claim 1, where the column selection circuitry comprises one or more column write devices and where the second column select signal is to enable a first column write device to couple a bitline to write driver circuitry.

### Claim 10 (depends on 1)

The storage device of claim 1, further comprising precharge circuitry to precharge a bitline.

### Claim 11 (depends on 10)

The storage device of claim 10, where the precharge circuitry is not activated between a read operation and a write operation in the first mode of operation.

### Claim 12 (depends on 1)

The storage device of claim 1, where the first control signal comprises two clock pulses and where the third control signal comprises a single pulse having a length substantially similar to the total length of the two clock pulses of the first control signal.

### Claim 13 (depends on 1)

The storage device of claim 1, where the read and write operation comprises an eviction and allocation operation.

### Claim 14 (depends on 1)

A non-transitory computer-readable medium to store computer-readable code for fabrication of the storage device of claim 1.

### Claim 15

A method of controlling a read operation and a write operation at a storage device, the storage device having:
core circuitry comprising one or more bitcells, each bitcell accessible via a corresponding bitline and wordline;
column selection circuitry to, responsive to a column select signal, select at least one bitcell via one or more bitlines;
wordline selection circuitry to, responsive to a wordline select signal, select the at least one bitcell via one or more wordlines; and
control circuitry to operate in a first mode or second mode, the method comprising:
providing, from the control circuitry operating in the first mode to the wordline selection circuitry, a first wordline select signal responsive to a first control signal;
providing, from the control circuitry operating in the first mode to the column selection circuitry, first and second column select signals responsive to a second control signal, and wherein:
the first column select signal is to control a read operation and the second column select signal is to control a write operation, and
a transition of the second control signal triggers the read operation to complete and simultaneously triggers the write operation to begin.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
providing, from the control circuitry operating in the second mode to the wordline selection circuitry, a second wordline select signal responsive to the first control signal;
providing, from the control circuitry operating in the second mode to the column selection circuitry, third and fourth column select signals responsive to the first control signal, and where the third column select signal is to control a read operation and where the fourth column select signal is to control a write operation.