# US 12,770,670 B2 · Operation method of ferroelectric memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,770,670 B2
- Document ID: US12770670B2
- Status: Granted
- Kind: B2
- Application number: 18/911,354
- Filed: 2024-10-10
- Published: 2026-04-16
- Granted: 2026-10-20
- Earliest claimed: 2024-10-10
- Assignees: Wuxi Smart Memories Technologies Co., Ltd.
- Applicants: Wuxi Smart Memories Technologies Co., Ltd.
- Inventors: Feng Pan; Ke Ma; Tong Feng
- Web page: https://patentgrep.com/patent/US12770670B2

## CPC

- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2273: {Reading or sensing circuits or methods}
- H10B 53/30: characterised by the memory core region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

According to one aspect, a method of operating a set of ferroelectric memory cells is provided. The method may include writing a first data bit having a first value to a first ferroelectric memory cell. The method may include writing a sign bit having the first value to second ferroelectric memory cell. The method may include receiving a read or a write-operation request. The method may include reading the sign bit from the second ferroelectric memory cell. The method may include, in response to the sign bit having a second value, inverting the first data bit from the second value to the first value. The method may include, in response to the sign bit having a second value, reading the first data bit with the first value from the first ferroelectric memory cell after the inverting.

## Claims

### Claim 1

A method of operating a set of ferroelectric memory cells, comprising:
writing a first data bit having a first value to a first ferroelectric memory cell of the set of ferroelectric memory cells at a first time;
writing a sign bit having the first value to second ferroelectric memory cell of the set of ferroelectric memory cells at the first time, the sign bit indicating a polarity of the first ferroelectric memory cell and the second ferroelectric memory cell;
receiving a read-operation request or a write-operation request for the first ferroelectric memory cell at a second time following the first time;
in response to the read-operation request or the write-operation request, reading the sign bit from the second ferroelectric memory cell at the second time; and
in response to the sign bit having a second value at the second time,
inverting the first data bit from the second value to the first value; and
reading the first data bit with the first value from the first ferroelectric memory cell after the inverting.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
in response to the sign bit having the first value at the second time, reading the first data bit with the first value from the first ferroelectric memory cell.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
in response to the write-operation request, inverting the sign bit from the first value to the second value.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
in response to the write-operation request, writing a second data bit having a second value to the first ferroelectric memory cell and the sign bit having the second value to the second ferroelectric memory cell.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second data bit having the second value is new data.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
in response to the read-operation request, inverting the first data bit from the first value to the second value.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
in response to the read-operation request, writing the first data bit having a second value to the first ferroelectric memory cell and the sign bit having the second value to the second ferroelectric memory cell.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first data bit having the second value and the sign bit having the second value are written to the first ferroelectric memory cell and the second ferroelectric memory cell, respectively, as part of a write-back operation.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first data bit having the second value is written to the first ferroelectric memory cell concurrent with the sign bit having the second value being written to the second ferroelectric memory cell.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
when the sign bit has the first value at the second time, the first data bit has a correct polarity, and
when the sign bit has the second value at the second time, the first data bit has an inverted polarity from actual data.

### Claim 11

A memory device, comprising:
a set of ferroelectric memory cells; and
a peripheral circuit coupled to the set of ferroelectric memory cells and configured to:
write a first data bit having a first value to a first ferroelectric memory cell of the set of ferroelectric memory cells at a first time;
write a sign bit having the first value to second ferroelectric memory cell of the set of ferroelectric memory cells at the first time, the sign bit indicating a polarity of the first ferroelectric memory cell and the second ferroelectric memory cell;
receive a read-operation request or a write-operation request for the first ferroelectric memory cell at a second time following the first time;
in response to the read-operation request or the write-operation request, read the sign bit from the second ferroelectric memory cell at the second time; and
in response to the sign bit having a second value at the second time,
invert the first data bit from the second value to the first value; and
read the first data bit with the first value from the first ferroelectric memory cell after the inverting.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the peripheral circuit is further configured to:
in response to the sign bit having the first value at the second time, read the first data bit with the first value from the first ferroelectric memory cell.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the peripheral circuit is further configured to:
in response to the write-operation request, invert the sign bit from the first value to the second value.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the peripheral circuit is further configured to:
in response to the write-operation request, write a second data bit having a second value to the first ferroelectric memory cell and the sign bit having the second value to the second ferroelectric memory cell.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the second data bit having the second value is new data.

### Claim 16 (depends on 11)

The memory device of claim 11, wherein the peripheral circuit is further configured to:
in response to the read-operation request, invert the first data bit from the first value to the second value.

### Claim 17 (depends on 11)

The memory device of claim 11, wherein the peripheral circuit is further configured to:
in response to the read-operation request, write the first data bit having a second value to the first ferroelectric memory cell and the sign bit having the second value to the second ferroelectric memory cell.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the first data bit having the second value and the sign bit having the second value are written to the first ferroelectric memory cell and the second ferroelectric memory cell, respectively, as part of a write-back operation.

### Claim 19 (depends on 17)

The memory device of claim 17, wherein the first data bit having the second value is written to the first ferroelectric memory cell concurrent with the sign bit having the second value being written to the second ferroelectric memory cell.

### Claim 20 (depends on 11)

The memory device of claim 11, wherein:
when the sign bit has the first value at the second time, the first data bit has a correct polarity, and
when the sign bit has the second value at the second time, the first data bit has an inverted polarity from actual data.