# US 12,770,667 B2 · Method for efficiently waking up ferroelectric memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,770,667 B2 - Document ID: US12770667B2 - Status: Granted - Kind: B2 - Application number: 18/766,808 - Filed: 2024-07-09 - Published: 2024-10-31 - Granted: 2026-10-20 - Earliest claimed: 2021-07-08 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Tzu-Yu Chen; Sheng-Hung Shih; Fu-Chen Chang; Kuo-Chi Tu; Wen-Ting Chu - Web page: https://patentgrep.com/patent/US12770667B2 ## CPC - G11C 11/221: {using ferroelectric capacitors} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells. ## Claims ### Claim 1 A method for waking up ferroelectric memory, comprising steps of: forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cell includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode, and the ferroelectric structure includes a cluster of vacancies or traps that obstruct reversals of electric dipoles around the cluster of vacancies or traps; and applying a voltage signal to the ferroelectric memory cell to induce an electric field in the ferroelectric structure, thereby spreading out the cluster of vacancies or traps, wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts, and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion. ### Claim 2 (depends on 1) The method according to claim 1, wherein the electric field in the ferroelectric structure, which is induced by the applying of the voltage signal, is in a range between 2×106 volts/cm and 6×106 volts/cm. ### Claim 3 (depends on 1) The method according to claim 1, wherein the ferroelectric structure has a thickness in a range from 5 nm to 20 nm, and the applying of the voltage signal results in a voltage across the ferroelectric structure ranging from 1 volt to 12 volts. ### Claim 4 (depends on 1) The method according to claim 1, wherein the voltage signal is applied in such a way that the wake-up voltage signal across the ferroelectric capacitor has a positive pulse group and a negative pulse group; wherein the positive pulse group includes a plurality of consecutive positive voltage pulses, and the negative pulse group includes a plurality of consecutive negative voltage pulses; and wherein one of the positive pulse group and the negative pulse group follows the other one of the positive pulse group and the negative pulse group. ### Claim 5 (depends on 4) The method according to claim 4, wherein each of the consecutive positive voltage pulses induces the electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm in magnitude, and each of the consecutive negative voltage pulses induces the electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm in magnitude. ### Claim 6 (depends on 4) The method according to claim 4, wherein the consecutive positive voltage pulses in the positive pulse group are different from each other in pulse width. ### Claim 7 (depends on 6) The method according to claim 6, wherein the consecutive negative voltage pulses in the negative pulse group are different from each other in pulse width. ### Claim 8 (depends on 6) The method according to claim 6, wherein the consecutive positive voltage pulses in the positive pulse group are different from each other in voltage magnitude. ### Claim 9 (depends on 8) The method according to claim 8, wherein the consecutive negative voltage pulses in the negative pulse group are different from each other in pulse width and voltage magnitude. ### Claim 10 (depends on 8) The method according to claim 8, wherein pulse widths of the consecutive positive voltage pulses are negatively correlated with voltage magnitudes of the consecutive positive voltage pulses. ### Claim 11 A method for waking up ferroelectric memory, comprising steps of: forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cell includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode; and applying a voltage signal to the ferroelectric memory cell to rise a percentage of molecules of a ferroelectric phase in the ferroelectric structure to a range from 50% to 100%, wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts, and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion. ### Claim 12 (depends on 11) The method according to claim 11, wherein the voltage signal induces an electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm. ### Claim 13 (depends on 11) The method according to claim 11, wherein the voltage signal is applied in such a way that the wake-up voltage signal across the ferroelectric capacitor has a plurality of voltage pulses; and wherein pulse widths of the voltage pulses are negatively correlated with voltage magnitudes of the voltage pulses. ### Claim 14 (depends on 13) The method according to claim 13, wherein the wake-up voltage signal across the ferroelectric capacitor has a positive pulse group and a negative pulse group; wherein the positive pulse group includes a plurality of consecutive positive voltage pulses, and the negative pulse group includes a plurality of consecutive negative voltage pulses; and wherein one of the positive pulse group and the negative pulse group follows the other one of the positive pulse group and the negative pulse group. ### Claim 15 A method for waking up ferroelectric memory, comprising steps of: forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cell includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode; and applying a voltage signal to the ferroelectric memory cell to increase each of a positive remnant polarization value and a negative remnant polarization value of the ferroelectric structure in magnitude, wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts, and wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion. ### Claim 16 (depends on 15) The method according to claim 15, wherein the voltage signal induces an electric field in the ferroelectric structure ranging between 2×106 volts/cm and 6×106 volts/cm. ### Claim 17 (depends on 15) The method according to claim 15, wherein the voltage signal is applied in such a way that the wake-up voltage signal across the ferroelectric capacitor has a plurality of voltage pulses; and wherein pulse widths of the voltage pulses are negatively correlated with voltage magnitudes of the voltage pulses. ### Claim 18 (depends on 14) The method according to claim 14, wherein the consecutive positive voltage pulses in the positive pulse group are different from each other in pulse width. ### Claim 19 (depends on 14) The method according to claim 14, wherein the consecutive positive voltage pulses in the positive pulse group are different from each other in voltage magnitude. ### Claim 20 (depends on 15) The method according to claim 15, wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive pulse group and a negative pulse group; wherein the positive pulse group includes a plurality of consecutive positive voltage pulses, and the negative pulse group includes a plurality of consecutive negative voltage pulses; and wherein one of the positive pulse group and the negative pulse group follows the other one of the positive pulse group and the negative pulse group.