# US 12,770,662 B2 · Nonvolatile memory device including multiple page buffers and operating method thereof

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- Number: US 12,770,662 B2
- Document ID: US12770662B2
- Status: Granted
- Kind: B2
- Application number: 18/626,349
- Filed: 2024-04-04
- Published: 2025-05-15
- Granted: 2026-10-20
- Earliest claimed: 2023-11-13
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Soo Yeol Chai
- Web page: https://patentgrep.com/patent/US12770662B2

## CPC

- G11C 7/109: {Control signal input circuits}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device including a memory cell array having multiple memory cells, multiple page buffers connected to the memory cells, and an enable control circuit configured to divide the page buffers into P groups, sequentially enable L groups among the P groups during an entry interval of an operation mode, and adjust a length of the entry interval of the operation mode based on a value of L, wherein P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

## Claims

### Claim 1

A memory device comprising:
a memory cell array including multiple memory cells;
multiple page buffers connected to the memory cells; and
an enable control circuit configured to divide the page buffers into P groups of page buffers,
sequentially enable L groups of page buffers among the P groups of page buffers during an entry interval of an operation mode for accessing the memory cell array, and
adjust a length of the entry interval of the operation mode based on a size of data accessed by the memory cell array according to a value of L,
wherein P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the enable control circuit comprises:
a signal generation unit configured to generate a selection control signal for selecting the value of L in response to a group selection signal;
a first toggling control unit configured to sequentially toggle first to L-th reference signals among P reference signals, in response to a start enable signal and the selection control signal;
a mode setting unit configured to enter the operation mode in response to the start enable signal, and configured to exit from the operation mode in response to the toggling of the L-th reference signal; and
a second toggling control unit configured to select L group enable signals among P group enable signals for enabling the P groups of page buffers, respectively, in response to the group selection signal during the entry interval of the operation mode, and configured to toggle the selected L group enable signals in response to the first to L-th reference signals, respectively.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the first toggling control unit comprises P flip-flops, selects an L-th flip-flop among the P flip-flops, in response to the selection control signal, and outputs L reference signals to output stages of a first flip-flop to the L-th flip-flop among the P flip-flops, respectively, in response to the start enable signal that is applied to an input stage of the first flip-flop.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the mode setting unit
activates an operation interval signal in response to the start enable signal, and
deactivates the operation interval signal in response to the toggling of the L-th reference signal among the L reference signals that are sequentially toggled.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the second toggling control unit
selects the L group enable signals corresponding to the group selection signal among the P group enable signals during an activation interval of the operation interval signal, and
sequentially toggles the L group enable signals in response to the L reference signals that are sequentially toggled, respectively.

### Claim 6

An operating method of a memory device comprising multiple page buffers that are connected to multiple memory cells, the operating method comprising:
dividing the page buffers into P groups of page buffers;
sequentially enabling L groups of page buffers among the P groups of page buffers during an entry interval of an operation mode for accessing the multiple memory cells; and
adjusting a length of the entry interval of the operation mode based on a size of data accessed by the multiple memory cells according to a value of L,
wherein P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

### Claim 7 (depends on 6)

The operating method of claim 6, wherein sequentially enabling the L groups of page buffers comprises:
generating a selection control signal for selecting the value of L in response to a group selection signal and P reference signals;
sequentially toggling first to L-th reference signals among the P reference signals in response to a start enable signal and the selection control signal; and
selecting L group enable signals among P group enable signals for enabling the P groups of page buffers, respectively, in response to the group selection signal during the entry interval of the operation mode, and toggling the selected L group enable signals in response to the first to L-th reference signals, respectively.

### Claim 8 (depends on 7)

The operating method of claim 7, wherein sequentially enabling the L groups of page buffers further comprises:
entering the operation mode in response to the start enable signal, and exiting from the operation mode in response to the toggling of the L-th reference signal.

### Claim 9 (depends on 8)

The operating method of claim 8, wherein sequentially toggling first to L-th reference signals comprises:
selecting an L-th flip-flop, among P flip-flops, in response to the selection control signal, and
outputting L reference signals to output stages of a first flip-flop to the L-th flip-flop among the P flip-flops, respectively, in response to the start enable signal that is applied to an input stage of the first flip-flop.

### Claim 10 (depends on 7)

The operating method of claim 7, wherein adjusting the length of the entry interval of the operation mode comprises
entering the operation mode by activating an operation interval signal in response to the start enable signal, and
exiting from the operation mode by deactivating the operation interval signal in response to the toggling of the L-th reference signal.

### Claim 11 (depends on 10)

The operating method of claim 10, wherein selecting L group enable signals comprises:
selecting the L group enable signals corresponding to the group selection signal among the P group enable signals during an activation interval of the operation interval signal, and
sequentially toggling the L group enable signals in response to the L reference signals that are sequentially toggled.