# US 12,770,575 B2 · Electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,770,575 B2 - Document ID: US12770575B2 - Status: Granted - Kind: B2 - Application number: 19/209,389 - Filed: 2025-05-15 - Published: 2026-02-12 - Granted: 2026-10-20 - Earliest claimed: 2024-08-12 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., LTD. - Inventors: Youngwan Seo; Junki Jeong; Junghwan Hwang - Web page: https://patentgrep.com/patent/US12770575B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0283: Arrangement of drivers for different directions of scanning - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract An electronic device includes a stage. The stage includes a node control circuit; a first transistor connected between a first power line and a first output node; a first capacitor connected between a gate electrode of the first transistor and the first output node; a second transistor connected between a first clock line and a second output node; a second capacitor connected between a gate electrode of the second transistor and the second output node; a third transistor connected between a second clock line and a third output node; a third capacitor connected between a gate electrode of the third transistor and the third output node; and a fourth transistor connected between a first node and the gate electrode of the first transistor, and maintained in a turn-on state in response to a first voltage. ## Claims ### Claim 1 An electronic device comprising: a plurality of pixels; a plurality of scan lines electrically connected to the plurality of pixels; and a stage electrically connected to corresponding scan lines of the plurality of scan lines to receive a first clock signal and a second clock signal, wherein the stage comprises: a node control circuit configured to control a voltage of a first node and a voltage of a second node; a first output circuit comprising a first transistor, which is connected between a first power line to which a first voltage is provided and a first output node, and a first capacitor, which is connected between a gate electrode of the first transistor and the first output node; a second output circuit comprising a second transistor, which is connected between a first clock line to which the first clock signal is provided and a second output node, and a second capacitor, which is connected between a gate electrode of the second transistor and the second output node; a third output circuit comprising a third transistor, which is connected between a second clock line to which the second clock signal is provided and a third output node and a third capacitor, which is connected between a gate electrode of the third transistor and the third output node; and a fourth transistor connected between the first node and the gate electrode of the first transistor, and configured to be maintained in a turn-on state in response to the first voltage. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein the first transistor, the second transistor, and the third transistor are controlled in response to a voltage of a third node. ### Claim 3 (depends on 1) The electronic device of claim 1, wherein the stage further comprises: a fifth transistor, which is connected between the first node and the gate electrode of the second transistor; and a sixth transistor, which is connected between the first node and the gate electrode of the third transistor. ### Claim 4 (depends on 3) The electronic device of claim 3, wherein the fifth transistor and sixth transistor are maintained in a turn-on state in response to the first voltage. ### Claim 5 (depends on 4) The electronic device of claim 4, further comprising a third clock line to which a third clock signal is provided and a fourth clock line to which a fourth clock signal is provided, wherein the first clock signal has a first turn-on period, the second clock signal has a second turn-on period, the third clock signal has a third turn-on period, and the fourth clock signal has a fourth turn-on period, wherein the first turn-on period and the third turn-on period do not overlap each other, and the second turn-on period and the fourth turn-on period do not overlap each other. ### Claim 6 (depends on 5) The electronic device of claim 5, wherein each of the fifth transistor and the sixth transistor further comprises a back gate electrode, wherein the back gate electrode of the fifth transistor is connected to the third clock line, and wherein the back gate electrode of the sixth transistor is connected to the fourth clock line. ### Claim 7 (depends on 5) The electronic device of claim 5, wherein the stage further comprises: a seventh transistor, which is connected between a second power line to which a second voltage having a lower level than the first voltage is provided and the gate electrode of the second transistor; and an eighth transistor, which is connected between the second power line and the gate electrode of the third transistor, wherein a gate electrode of the seventh transistor and a gate electrode of the eighth transistor are connected to the third clock line. ### Claim 8 (depends on 7) The electronic device of claim 7, wherein the stage further comprises a ninth transistor, which is connected between the first node and a fourth node, wherein one end of the fifth transistor and one end of the sixth transistor are connected to the fourth node, and a gate electrode of the ninth transistor is connected to the fourth click line. ### Claim 9 (depends on 1) The electronic device of claim 1, wherein the first output circuit outputs a first output signal having a first output turn-on period, the second output circuit outputs a second output signal having a second output turn-on period, and the third output circuit outputs a third output signal having a third output turn-on period, wherein each of the second output turn-on period and third output turn-on period overlaps the first output turn-on period. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein the plurality of pixels comprise a first pixel and a second pixel spaced apart from the first pixel, wherein the first output signal is transferred to the first pixel and the second pixel, the second output signal is transferred to the first pixel, and the third output signal is transferred to the second pixel. ### Claim 11 (depends on 1) The electronic device of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are an N-type transistor. ### Claim 12 (depends on 1) The electronic device of claim 1, further comprising a second power line to which a second voltage having a lower level than the first voltage is provided, wherein the first output circuit further comprises a first pull-down transistor, which is connected between the second power line and the first transistor, the second output circuit further comprises a second pull-down transistor, which is connected between the second power line and the second transistor, and the third output circuit further comprises a third pull-down transistor, which is connected between the second power line and the third transistor, wherein the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor are controlled in response to the voltage of the second node. ### Claim 13 (depends on 12) The electronic device of claim 12, further comprising: a third power line to which a third voltage having a lower level than each of the first voltage and second voltage is provided; and a carry clock line to which a carry clock signal is provided, wherein the stage further comprises a carry circuit comprising a first carry transistor and a second carry transistor, which are connected between the carry clock line to which the carry clock signal is provided and the third power line. ### Claim 14 An electronic device comprising: a first pixel; a second pixel spaced apart from the first pixel; a first write scan line electrically connected to the first pixel; a second write scan line electrically connected to the second pixel; a compensation scan line electrically connected to the first pixel and second pixel; and a stage configured to output a first write scan signal to the first write scan line, output a second write scan signal to the second write scan line, and output a compensation scan signal to the compensation scan line, wherein the stage comprises: a first transistor, which is connected between a first power line to which a first voltage is provided and a first output node; a second transistor, which is connected between a first clock line to which a first clock signal is provided and a second output node; a third transistor, which is connected between a second clock line to which a second clock signal is provided and a third output node; and a fourth transistor connected between a first node and a gate electrode of the first transistor, and configured to be maintained in a turn-on state in response to the first voltage. ### Claim 15 (depends on 14) The electronic device of claim 14, further comprising a second power line to which a second voltage having a lower level than the first voltage is provided, wherein the stage further comprises: a first pull-down transistor connected between the second power line and the first transistor, a second pull-down transistor connected between the second power line and the second transistor, and a third pull-down transistor connected between the second power line and the third transistor, wherein the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor are controlled in response to a voltage of a second node. ### Claim 16 (depends on 15) The electronic device of claim 15, wherein the first transistor, the second transistor, and the third transistor are controlled in response to a voltage of a third node. ### Claim 17 (depends on 14) The electronic device of claim 14, wherein the stage further comprises: a fifth transistor connected between the first node and a gate electrode of the second transistor; and a sixth transistor connected between the first node and a gate electrode of the third transistor, wherein the fifth transistor and the sixth transistor are maintained in a turn-on state in response to the first voltage. ### Claim 18 (depends on 17) The electronic device of claim 17, wherein each of the fifth transistor and the sixth transistor further comprises a back gate electrode, wherein the back gate electrode of the fifth transistor is connected to a third clock line, and the back gate electrode of the sixth transistor is connected to a fourth clock line. ### Claim 19 (depends on 17) The electronic device of claim 17, wherein the stage further comprises: a first initializing transistor connected between a second power line to which a second voltage having a lower level than the first voltage is provided and the gate electrode of the second transistor; and a second initializing transistor connected between the second power line and the gate electrode of the third transistor, wherein a gate electrode of the first initializing transistor and a gate electrode of the second initializing transistor are connected to a third clock line. ### Claim 20 (depends on 19) The electronic device of claim 19, wherein the stage further comprises a blocking transistor connected between the first node and a fourth node, wherein one end of the fifth transistor and one end of the sixth transistor are connected to the fourth node, and a gate electrode of the blocking transistor is connected to a fourth clock line.