# US 12,770,554 B2 · Scan driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,770,554 B2 - Document ID: US12770554B2 - Status: Granted - Kind: B2 - Application number: 19/083,438 - Filed: 2025-03-19 - Published: 2025-07-03 - Granted: 2026-10-20 - Earliest claimed: 2019-08-28 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Yang Hwa Choi; Bo Yong Chung - Web page: https://patentgrep.com/patent/US12770554B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2310/0264: Details of driving circuits - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node. ## Claims ### Claim 1 A scan driver comprising: stage groups each including a first scan stage and a second scan stage, wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group, wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor, wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a fourth control signal of a fourth control line, and wherein the first scan stage includes: a second transistor including a first electrode electrically connected to a first previous carry line, a second electrode electrically connected to a first Q node, and a gate electrode electrically connected to the first electrode of the second transistor; a ninth transistor including a first electrode electrically connected to a first carry clock line, a second electrode electrically connected to a first carry line, and a gate electrode electrically connected to the first Q node; a first transistor including a first electrode electrically connected to a first scan clock line, a second electrode electrically connected to a first scan line, and a gate electrode electrically connected to the first Q node; a sixth transistor including a first electrode electrically connected to a first node, a second electrode electrically connected to the first Q node, and a gate electrode electrically connected to a third control line; a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to the first node, and a gate electrode; a nineteenth transistor electrically connected to the gate electrode of the fifth transistor and including a gate electrode electrically connected to the fourth control line; a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor, and wherein the first capacitor is electrically connected between the second control line and the gate electrode of the fifth transistor. ### Claim 2 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: a thirteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; and a fourteenth transistor including a first electrode electrically connected to the first carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage. ### Claim 3 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: a second capacitor electrically connected between the first Q node and the first scan line; a seventeenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node; and an eighteenth transistor including a first electrode electrically connected to the first scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node of the second scan stage. ### Claim 4 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: an eleventh transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node; a twelfth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node of the second scan stage; a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first QB node; and a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the first QB node, and a gate electrode electrically connected to the first previous carry line. ### Claim 5 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node; and a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to a second Q node of the second scan stage. ### Claim 6 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; and a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a first QB node, and a gate electrode electrically connected to the third control line. ### Claim 7 (depends on 1) The scan driver of claim 1, wherein the first scan stage further includes: a tenth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line. ### Claim 8 (depends on 1) The scan driver of claim 1, wherein the second transistor includes a first sub-transistor electrically connected between the first previous carry line and a third node and a second sub-transistor electrically connected between the third node and the first Q node, wherein the first scan stage further includes a seventh transistor including a gate electrode electrically connected to the first Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node. ### Claim 9 (depends on 1) The scan driver of claim 1, wherein the second scan stage includes: wherein the first scan stage includes: a forty-ninth transistor including a first electrode electrically connected to a second previous carry line, a second electrode electrically connected to a second Q node, and a gate electrode electrically connected to the first electrode of the forty-ninth transistor; a thirty-second transistor including a first electrode electrically connected to a second carry clock line, a second electrode electrically connected to a second carry line, and a gate electrode electrically connected to the first Q node; a thirtieth transistor including a first electrode electrically connected to a second scan clock line, a second electrode electrically connected to a second scan line, and a gate electrode electrically connected to the second Q node; a forty-seventh transistor including a first electrode electrically connected to a second node, a second electrode electrically connected to the second Q node, and a gate electrode electrically connected to the third control line; and a fiftieth transistor including a gate electrode electrically connected to the second Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to a fourth node, and wherein the forty-ninth transistor includes a third sub-transistor electrically connected between the second Q node and the fourth node and a fourth sub-transistor electrically connected between the fourth node and the second previous carry line. ### Claim 10 (depends on 9) The scan driver of claim 9, wherein the second scan stage further includes: a thirty-ninth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and a fortieth transistor including a first electrode electrically connected to the second carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node. ### Claim 11 (depends on 9) The scan driver of claim 9, wherein the second scan stage further includes: a fourth capacitor electrically connected between the second Q node and the second scan line; a forty-third transistor including a first electrode electrically connected to the second scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a first QB node of the first scan stage; and a forty-fourth transistor including a first electrode electrically connected to the scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a second QB node. ### Claim 12 (depends on 9) The scan driver of claim 9, wherein the second scan stage further includes: a thirty-third transistor including a first electrode electrically connected to the second Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a first QB node of the first scan stage; a thirty-fourth transistor including a first electrode electrically connected to the first Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a second QB node; a fifty-third transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second QB node; a fifty-fourth transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second previous carry line, a thirty-fifth transistor including a first electrode electrically connected to a sixth control line, a second electrode, and a gate electrode electrically connected to the sixth control line; a thirty-sixth transistor including a first electrode electrically connected to the sixth control line, a second electrode electrically connected to the second QB node, and a gate electrode electrically connected to the second electrode of the thirty-fifth transistor; a thirty-seventh transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the first Q node of the first scan stage; and a thirty-eighth transistor including a first electrode electrically connected to the second electrode of the thirty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the second Q node. ### Claim 13 A scan driver comprising: stage groups each including a first scan stage and a second scan stage, wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group, wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor, wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and wherein each of the stage groups includes: a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode; the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor; and a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and wherein each of the first and second scan stages includes: a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor; a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node; a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node; a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line; a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line; and a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor. ### Claim 14 (depends on 13) The scan driver of claim 13, wherein the third transistor includes: a fifth sub-transistor including a gate electrode electrically connected to the first control line and a first electrode electrically connected to the previous carry line; and a sixth sub-transistor including a gate electrode electrically connected to the first control line, a first electrode electrically connected to a second electrode of the fifth sub-transistor, and a second electrode electrically connected to the gate electrode of the fifth transistor, and wherein each of the stage groups further includes: a twenty-ninth transistor including a gate electrode electrically connected to the second electrode of the sixth sub-transistor, a first electrode electrically connected to the first electrode of the sixth sub-transistor, and a second electrode electrically connected to the second control line. ### Claim 15 (depends on 13) The scan driver of claim 13, wherein each of the first and second scan stages further includes: a thirteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; and a fourteenth transistor including a first electrode electrically connected to the corresponding carry line, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage. ### Claim 16 (depends on 13) The scan driver of claim 13, wherein each of the first and second scan stages further includes: a second capacitor electrically connected between the Q node and the corresponding scan line; a seventeenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to a second power line, and a gate electrode electrically connected to a QB node of the first scan stage; and an eighteenth transistor including a first electrode electrically connected to the corresponding scan line, a second electrode electrically connected to the second power line, and a gate electrode electrically connected to a QB node of the second scan stage. ### Claim 17 (depends on 13) The scan driver of claim 13, wherein each of the first and second scan stages further includes: an eleventh transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a QB node of the first scan stage; a twelfth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a QB node of the second scan stage; a twenty-first transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the QB node, and a gate electrode electrically connected to a corresponding QB node of one of the first and second scan stages; and a twenty-second transistor including a first electrode electrically connected to the first power line, a second electrode electrically connected to the corresponding QB node, and a gate electrode electrically connected to the corresponding previous carry line. ### Claim 18 (depends on 13) The scan driver of claim 13, wherein each of the first and second scan stages further includes: a twenty-seventh transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to a third power line, and a gate electrode electrically connected to the Q node of the first scan stage; and a twenty-eighth transistor including a first electrode electrically connected to the second electrode of the twenty-fifth transistor, a second electrode electrically connected to the third power line, and a gate electrode electrically connected to the Q node of the second scan stage. ### Claim 19 (depends on 13) The scan driver of claim 13, wherein each of the first and second scan stages further includes: a twenty-third transistor including a first electrode electrically connected to a first power line, a second electrode, and a gate electrode electrically connected to the gate electrode of the fifth transistor; a twenty-fourth transistor including a first electrode electrically connected to the second electrode of the twenty-third transistor, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the third control line a tenth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to a first power line, and a gate electrode electrically connected to a next carry line; and a twentieth transistor including a first electrode electrically connected to the Q node, a second electrode electrically connected to the first power line, and a gate electrode electrically connected to a fourth control line. ### Claim 20 (depends on 13) The scan driver of claim 13, wherein the second transistor includes a first sub-transistor electrically connected between the corresponding previous carry line and a third node and a second sub-transistor electrically connected between the third node and the Q node, wherein each of the first and second scan stages further includes a seventh transistor including a gate electrode electrically connected to the Q node, a first electrode electrically connected to the second control line, and a second electrode electrically connected to the third node.