# US 12,770,213 B2 · Efficient hybrid-graphics pipeline

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- Number: US 12,770,213 B2
- Document ID: US12770213B2
- Status: Granted
- Kind: B2
- Application number: 18/763,755
- Filed: 2024-07-03
- Published: 2026-01-08
- Granted: 2026-10-20
- Earliest claimed: 2024-07-03
- Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Applicants: Advanced Micro Devices, Inc.; ATI Technologies ULC
- Inventors: Yuping Shen; Adeel Nasim Syed; Anthony Wai Lap Koo; Bohan Shi; Felipe Sander Pereira Clark; ZhuoQiao Liang; HongYu Lu; Michael Gharbharan; Nitant Patel; YongYong Wu
- Web page: https://patentgrep.com/patent/US12770213B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 21/6209: {to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus and method for efficiently managing jobs of a workload performed among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes a first processing node and a second processing node that together render and present video frame data. The graphics application holds the start of processing the next video frame until the first processing node receives result data for the current video frame from the second processing node and presents the video frame data. To remove latency, once the result data is generated, the first processing node performs a mocked present job visible to the operating system scheduler but sends no data to the display controller. The rendering of the next video frame begins, and the first processing node later presents the result data to the display controller.

## Claims

### Claim 1

An apparatus comprising:
circuitry configured to:
send a first task to a processing node to render a first video frame;
receive a first indication that specifies the processing node has generated rendered data corresponding to the first video frame; and
send a second task to the processing node to render a second video frame, wherein the second task is sent prior to initiating execution of a present operation that sends, to a display controller, rendered data corresponding to the first video frame.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1, wherein in response to the first indication, the circuitry is further configured to send the second task to the processing node to render the second video frame.

### Claim 3 (depends on 1)

The apparatus as recited in claim 1, wherein the circuitry is further configured to generate a second indication that indicates the present operation has completed, prior to completion of the present operation.

### Claim 4 (depends on 3)

The apparatus as recited in claim 3, wherein in response to the second indication, the circuitry is configured to send the second task to the processing node to render the second video frame.

### Claim 5 (depends on 3)

The apparatus as recited in claim 3, wherein in response to receiving a third indication that the apparatus has received the rendered data corresponding to the first video frame, the circuitry is configured to initiate execution of the present operation to send the rendered data to the display controller.

### Claim 6 (depends on 5)

The apparatus as recited in claim 5, wherein the circuitry comprises a first processing circuit and a second processing circuit, wherein:
the first processing circuit is configured to execute an operating system scheduler; and
the second processing circuit is configured to assign at least one or more wait synchronization points to a private queue storing instructions to be executed by the second processing circuit executing a graphics driver and not executed by the first processing circuit executing the operating system scheduler.

### Claim 7 (depends on 6)

The apparatus as recited in claim 6, wherein the second processing circuit is further configured to:
unblock a first wait synchronization point in the private queue, responsive to the first indication; and
generate the second indication based at least in part on the first wait synchronization point being unblocked.

### Claim 8

A method, comprising:
sending, by circuitry of a first processing node, a first task to a second processing node to render a first video frame;
receiving, by the first processing node, a first indication that specifies the second processing node has generated rendered data corresponding to the first video frame; and
sending, by the first processing node, a second task to the second processing node to render a second video frame, wherein the second task is sent prior to initiating execution of a present operation that sends, to a display controller, rendered data corresponding to the first video frame.

### Claim 9 (depends on 8)

The method as recited in claim 8, wherein in response to the first indication, the method further comprises sending, by the first processing node, the second task to the second processing node to render the second video frame.

### Claim 10 (depends on 9)

The method as recited in claim 9, wherein in response to receiving an indication that the first node has received the rendered data corresponding to the first video frame, the method further comprises initiating execution of the present operation, by the first processing node, to send the rendered data to the display controller.

### Claim 11 (depends on 8)

The method as recited in claim 8, further comprising generating, by the first processing node, a second indication that indicates the present operation has completed, prior to completion of the present operation.

### Claim 12 (depends on 10)

The method as recited in claim 10, wherein in response to the second indication, the method further comprises sending, by the first processing node, the second task to the second processing node to render the second video frame.

### Claim 13 (depends on 11)

The method as recited in claim 11, further comprising:
executing, by a first processing circuit of the circuitry of the first processing node, an operating system scheduler; and
assigning, by a second processing circuit of the circuitry of the first processing node, at least one or more wait synchronization points to a private queue storing instructions to be executed by the second processing circuit executing a graphics driver and not executed by the first processing circuit executing the operating system scheduler.

### Claim 14 (depends on 13)

The method as recited in claim 13, further comprising:
unblocking, by the second processing circuit, a first wait synchronization point in the private queue, responsive to the first indication; and
generating, by the second processing circuit, the second indication based at least in part on the first wait synchronization point being unblocked.

### Claim 15

A computing system comprising:
a first processing node comprising circuitry configured to execute tasks; and
a second processing node comprising circuitry configured to execute tasks; and
wherein the first processing node comprises:
circuitry configured to:
send a first task to the second processing node to render a first video frame;
receive a first indication that specifies the second processing node has generated rendered data corresponding to the first video frame; and
send a second task to the processing node to render a second video frame, wherein the second task is sent prior to initiating execution of a present operation that sends, to a display controller, rendered data corresponding to the first video frame.

### Claim 16 (depends on 15)

The computing system as recited in claim 15, wherein in response to the first indication, the circuitry is further configured to send the second task to the second processing node to render the second video frame.

### Claim 17 (depends on 16)

The computing system as recited in claim 16, wherein in response to receiving an indication that the first node has received the rendered data corresponding to the first video frame, the circuitry is configured to initiate execution of the present operation to send the rendered data to the display controller.

### Claim 18 (depends on 15)

The computing system as recited in claim 15, wherein the circuitry is further configured to generate a second indication that indicates the present operation has completed, prior to completion of the present operation.

### Claim 19 (depends on 17)

The computing system as recited in claim 17, wherein in response to the second indication, the circuitry is configured to send the second task to the second processing node to render the second video frame.

### Claim 20 (depends on 18)

The computing system as recited in claim 18, wherein the circuitry comprises a first processing circuit and a second processing circuit, wherein:
the first processing circuit is configured to execute an operating system scheduler; and
the second processing circuit is configured to assign at least one or more wait synchronization points to a private queue storing instructions to be executed by the second processing circuit executing a graphics driver and not executed by the first processing circuit executing the operating system scheduler.