# US 12,769,908 B2 · Auto compaction tool for electronic design automation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,769,908 B2 - Document ID: US12769908B2 - Status: Granted - Kind: B2 - Application number: 17/992,881 - Filed: 2022-11-22 - Published: 2023-06-01 - Granted: 2026-10-20 - Earliest claimed: 2021-11-28 - Assignees: D2S, Inc. - Applicants: D2S, Inc. - Inventors: Donald Oriordan; Akira Fujimura; George Janac - Web page: https://patentgrep.com/patent/US12769908B2 ## CPC - G06F 30/31: Design entry, e.g. editors specifically adapted for circuit design - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06N 3/08: Learning methods - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network. ## Claims ### Claim 1 A method for compacting an integrated circuit (IC) design layout comprising a plurality of components, the method comprising for the design layout, iteratively: performing a compaction operation to compact the design layout; producing expected manufactured shapes of a set of routes in the compacted design layout; and using the expected manufactured shapes to assess whether another compaction operation should be performed, wherein producing the expected manufactured shapes comprises using a machine-trained network to produce a multi-contour display for each of a plurality of routes, each particular multi-contour display of each particular route in the plurality of routes representing a range of expected manufactured shapes for the particular route and having a plurality of contours corresponding to a plurality of variations of a parameter associated with a manufacturing process that is used to produce an IC from the IC design layout. ### Claim 2 (depends on 1) The method of claim 1, wherein the pluralities of contours for the plurality of routes comprise a first set of contours corresponding to a first variation of the manufacturing process parameter and a second set of contours corresponding to a second variation of the manufacturing process parameter. ### Claim 3 (depends on 1) The method of claim 1, wherein using the machine-trained network comprises using the machine-trained network to produce a plurality of pixel-based images representing the design layout after a manufacturing process has been performed using the design layout in order to manufacture a semiconductor die based on the design layout, the method further comprising generating, from the pixel-based definition of each image, the plurality of contours for each route in the plurality of routes. ### Claim 4 (depends on 1) The method of claim 1, wherein the machine-trained network is a neural network. ### Claim 5 (depends on 1) The method of claim 1, wherein the manufacturing process is a mask making process and the parameter relates to dosage used during mask making process. ### Claim 6 (depends on 1) The method of claim 1, wherein the manufacturing process is a wafer production process and the parameter relates to one of depth of focus and strength of exposure used during the wafer production process. ### Claim 7 (depends on 1) The method of claim 1, wherein the pluralities of contours for the plurality of routes comprise a first set of contours relating to a maximum variation of the manufacturing process parameter and a second set of contours relating to a minimum variation of the manufacturing process parameter. ### Claim 8 (depends on 7) The method of claim 7, wherein the pluralities of contours for the plurality of routes further comprise a third set of contours relating to a nominal variation of the manufacturing process parameter. ### Claim 9 (depends on 1) The method of claim 1, wherein the pluralities of contours for the plurality of routes comprise a first set of contours relating to a maximum variation of the manufacturing process parameter and a second set of contours relating to a nominal variation of the manufacturing process parameter. ### Claim 10 A non-transitory machine readable medium storing a program that when executed by one or more processing units of a computer compacts an integrated circuit (IC) design layout, the design layout comprising a plurality of components, the program comprising sets of instructions for: iteratively: performing a compaction operation to compact the design layout; producing expected manufactured shapes of a set of routes in the compacted design layout by using a machine-trained network to produce a multi-contour display for each of a plurality of routes, each particular multi-contour display of each particular route in the plurality of routes representing a range of expected manufactured shapes for the particular route and having a plurality of contours corresponding to a plurality of variations of a parameter associated with a manufacturing process that is used to produce an IC from the IC design layout; and using the expected manufactured shapes to assess whether another compaction operation should be performed. ### Claim 11 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the expected manufactured shapes of the set of routes represent the shapes of the set of routes after a series of manufacturing operations are performed to produce an IC from the design layout. ### Claim 12 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the set of instructions for using the expected manufactured shapes comprises a set of instructions for performing design rule check (DRC) on the design layout based on the produced expected manufactured shapes. ### Claim 13 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the pluralities of contours for the plurality of routes comprise a first set of contours corresponding to a first variation of the manufacturing process parameter and a second set of contours corresponding to a second variation of the manufacturing process parameter. ### Claim 14 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the set of instructions for using the machine-trained network comprises a set of instructions for using the machine-trained network to produce a plurality of pixel-based images representing the design layout after a manufacturing process has been performed using the design layout in order to manufacture a semiconductor die based on the design layout, the program further comprising a set of instructions for generating, from the pixel-based definition of each image, the plurality of contours for each route in the plurality of routes. ### Claim 15 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the manufacturing process is a wafer simulation process and the parameter relates to one of depth of focus and strength of exposure used during the wafer production process. ### Claim 16 (depends on 10) The non-transitory machine readable medium of claim 10, wherein the pluralities of contours for the plurality of routes comprise a first set of contours relating to a maximum variation of the manufacturing process parameter and a second set of contours relating to a minimum variation of the manufacturing process parameter.