# US 12,769,683 B2 · Serial peripheral interface with in-band interrupts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,769,683 B2 - Document ID: US12769683B2 - Status: Granted - Kind: B2 - Application number: 18/905,996 - Filed: 2024-10-03 - Published: 2026-04-09 - Granted: 2026-10-20 - Earliest claimed: 2024-10-03 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Balaji Bhaskar Kulkarni; Manish Rajendra Mehta; Sumeet Kumar Sahu - Web page: https://patentgrep.com/patent/US12769683B2 ## CPC - G06F 13/26: with priority control - G06F 9/30101: {Special purpose registers} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various aspects of the present disclosure generally relate to integrated circuits. In some aspects, a first device may identify an incoming request. The first device may transmit, to a second device via a serial peripheral interface (SPI) with in-band interrupts (IBIs), an interrupt based at least in part on the incoming request, wherein the interrupt is associated with a channel descriptor, and wherein the channel descriptor is unique per use case and across a plurality of SPI input/output (I/O) channels. Numerous other aspects are described. ## Claims ### Claim 1 A first device, comprising: one or more components configured to: identify an incoming request; and transmit, to a second device via a serial peripheral interface (SPI) with in-band interrupts (IBIs), an interrupt based at least in part on the incoming request, wherein the interrupt is associated with a channel descriptor, wherein the channel descriptor is unique per use case and across a plurality of SPI input/output (I/O) channels, and wherein the first device supports multiple use cases on a same SPI I/O channel. ### Claim 2 (depends on 1) The first device of claim 1, wherein the first device supports the multiple use cases on the same SPI I/O channel based at least in part on different channel descriptors. ### Claim 3 (depends on 1) The first device of claim 1, wherein the one or more components are further configured to: maintain a channel configuration register per SPI I/O channel, wherein the channel configuration register indicates, for each use case, the channel descriptor and a requested priority, wherein the channel descriptor is unique per each use case across the plurality of SPI I/O channels, and wherein the requested priority is configurable per use case. ### Claim 4 (depends on 1) The first device of claim 1, wherein the one or more components are further configured to: check a channel configuration register based at least in part on the incoming request; determine that the multiple use cases are supported on an SPI I/O channel, of the plurality of SPI I/O channels, wherein the SPI I/O channel comprises the same SPI I/O channel; check a status of a transmit buffer by reading a channel status register; and update the channel descriptor to indicate that an outgoing buffer is associated with a certain use case of the multiple use cases. ### Claim 5 (depends on 1) The first device of claim 1, wherein the SPI with IBIs is a quad SPI (QSPI) with IBIS. ### Claim 6 (depends on 1) The first device of claim 1, wherein the incoming request is associated with a write operation. ### Claim 7 (depends on 1) The first device of claim 1, wherein the first device is a system-on-chip (SOC) and the second device is a controller. ### Claim 8 A first device, comprising: one or more components configured to: receive, from a second device via a serial peripheral interface (SPI) with in-band interrupts (IBIs), an interrupt; identify, based at least in part on an interrupt status register bank, aggregate information for pending interrupts across a plurality of SPI input/output (I/O) channels, wherein the aggregate information includes priority information associated with the pending interrupts; and process the interrupt based at least in part on the aggregate information. ### Claim 9 (depends on 8) The first device of claim 8, wherein the first device supports interrupts for multiple use cases associated with a same SPI I/O channel, of the plurality of SPI I/O channels, based at least in part on interrupt priority. ### Claim 10 (depends on 8) The first device of claim 8, wherein the one or more components are further configured to: maintain the interrupt status register bank, wherein the interrupt status register bank indicates, for each use case of a plurality of use cases, a channel descriptor and an interrupt priority, wherein the channel descriptor is unique per each use case across the plurality of SPI I/O channels, and the interrupt status register bank indicates the aggregate information across the plurality of SPI I/O channels and the plurality of use cases. ### Claim 11 (depends on 8) The first device of claim 8, wherein the one or more components are further configured to: discover one or more use cases supported with each SPI I/O channel, of the plurality of SPI I/O channels, using one or more channel status registers associated with the interrupt status register bank. ### Claim 12 (depends on 8) The first device of claim 8, wherein the one or more components are further configured to: process the interrupt based at least in part on the interrupt having a highest priority among a plurality of the pending interrupts, as indicated by the aggregate information. ### Claim 13 (depends on 8) The first device of claim 8, wherein the first device is a system-on-chip (SOC) and the second device is a controller. ### Claim 14 A first device, comprising: one or more components configured to: receive, from a second device via a serial peripheral interface (SPI) with in-band interrupts (IBIs), an interrupt; and evaluate a priority of the interrupt in accordance with a channel configuration register, wherein the channel configuration register contains one or more use cases associated with each SPI input/output (I/O) channel of a plurality of SPI I/O channels. ### Claim 15 (depends on 14) The first device of claim 14, wherein interrupt priority is configured across the plurality of SPI I/O channels, and wherein the priority of the interrupt is evaluated in accordance with the interrupt priority during a processing of the interrupt. ### Claim 16 (depends on 14) The first device of claim 14, wherein the one or more components are further configured to: read the channel configuration register, wherein the channel configuration register is published by the first device; determine an interrupt priority per use case based at least in part on the channel configuration register; and update an interrupt priority configuration register bank across the one or more use cases supported on the plurality of SPI I/O channels. ### Claim 17 (depends on 14) The first device of claim 14, wherein the one or more components are further configured to: maintain the channel configuration register per SPI I/O channel, wherein the channel configuration register indicates, for each use case, a channel descriptor and a requested priority, wherein the channel descriptor is unique per each use case across the plurality of SPI I/O channels, and wherein the requested priority is configurable per use case. ### Claim 18 (depends on 14) The first device of claim 14, wherein the one or more components are further configured to: maintain an interrupt priority configuration register bank, wherein the interrupt priority configuration register bank indicates, for each use case, a channel descriptor and an interrupt priority, and wherein the channel descriptor is unique per each use case across the plurality of SPI I/O channels. ### Claim 19 (depends on 14) The first device of claim 14, wherein the first device is a system-on-chip (SOC) and the second device is a controller. ### Claim 20 A first device, comprising: one or more components configured to: identify a packet associated with a serial peripheral interface (SPI) with in-band interrupts (IBIs) between the first device and a second device; and validate, using an access policy manager, one or more properties associated with the packet to ensure that a secure use case is partitioned from a non-secure use case across a plurality of SPI input/output (I/O) channels. ### Claim 21 (depends on 20) The first device of claim 20, wherein the first device is configured to support secure use cases and non-secure use cases over the SPI with IBIs. ### Claim 22 (depends on 20) The first device of claim 20, wherein the packet is a transmit (Tx) packet. ### Claim 23 (depends on 20) The first device of claim 20, wherein the packet is a receive (Rx) packet. ### Claim 24 (depends on 20) The first device of claim 20, wherein the one or more properties include one or more of a channel descriptor, a security attribute, or an address, wherein the channel descriptor uniquely identifies a type of use case across an SPI I/O channel of the plurality of SPI I/O channels, wherein the security attribute indicates a secure attribute or a non-secure attribute, and wherein the address is included in a range of addresses that are allowed to be accessed by a certain use case in either a transmit (Tx) direction or a receive (Rx) direction. ### Claim 25 (depends on 20) The first device of claim 20, wherein the secure use case is associated with a first SPI I/O channel of the plurality of SPI I/O channels, and wherein the non-secure use case is associated with a second SPI I/O channel of the plurality of SPI I/O channels. ### Claim 26 (depends on 20) The first device of claim 20, wherein the one or more components are further configured to: maintain, via the access policy manager, the one or more properties for each use case of a plurality of use cases and across the plurality of SPI I/O channels. ### Claim 27 (depends on 20) The first device of claim 20, wherein the first device is a system-on-chip (SOC) and the second device is a controller.