# US 12,769,464 B2 · Memory access latency estimation method and memory access latency estimation system for estimating an access latency of a memory according to a plurality of coefficients and a plurality of indexes

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- Number: US 12,769,464 B2
- Document ID: US12769464B2
- Status: Granted
- Kind: B2
- Application number: 18/642,859
- Filed: 2024-04-23
- Published: 2024-10-31
- Granted: 2026-10-20
- Earliest claimed: 2023-04-25
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Chih-Chieh Chang; You-Hong Sun; Wen-Hsun Lin; Chia-Ching Chang
- Web page: https://patentgrep.com/patent/US12769464B2

## CPC

- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0673: {Single storage device}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory access latency estimation method includes measuring a first access latency of a first access operation of a first memory, measuring a plurality of first indexes of the first memory corresponding to the first access operation, using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients, using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation.

## Claims

### Claim 1

A memory access latency estimation method of a memory access latency estimation system, the memory access latency estimation system comprising a first monitor, a plurality of second monitors, and a processor, the processor being hardware-implemented, the processor comprising a member selected from a group comprising a central processing unit (CPU), a graphic processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application specific integrated circuit (ASIC), a deep learning processing unit (DPU), a vector processing unit (VPU), and a microprocessor, the memory access latency estimation method comprising:
measuring, by the first monitor, a first access latency of a first access operation of a first memory, wherein the first memory comprises a dynamic random-access memory;
measuring, by the plurality of second monitors, a plurality of first indexes of the first memory corresponding to the first access operation;
using, by the processor, a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency;
adjusting, by the processor using a machine learning model implemented in hardware circuitry of the processor, the plurality of first coefficients to generate a plurality of updated first coefficients;
using, by the processor, the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency; and
using, by the processor, the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation;
wherein number and types of the plurality of first indexes are the same as number and types of the plurality of second indexes, the plurality of second indexes are corresponding to the second access operation, and the first access operation precedes the second access operation.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
determining, by the processor, if a difference of the first estimated latency and the first access latency is smaller than a threshold; and
if the difference is not smaller than the threshold, the processor adjusting the plurality of updated first coefficients to adjust the first estimated latency to be closer to the first access latency and reduce the difference.

### Claim 3 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a bandwidth of the first memory.

### Claim 4 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a reciprocal of an operation frequency of the first memory.

### Claim 5 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a reciprocal of an operation frequency of an interface for the first memory.

### Claim 6 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a reciprocal of a parameter corresponding to a transaction priority.

### Claim 7 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a parameter corresponding to variety of access patterns.

### Claim 8 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a squared value of the bandwidth of the first memory.

### Claim 9 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a ratio of a frequency of the first memory to a frequency of an interface.

### Claim 10 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises square of a ratio of a frequency of the first memory to a frequency of an interface.

### Claim 11 (depends on 1)

The method of claim 1, wherein at least one of the plurality of first indexes comprises a ratio of a first value to a second value, the first value is a smaller one of a number of read operations and a number of write operations, and the second value is a larger one of the number of read operations and the number of write operations.

### Claim 12 (depends on 1)

The method of claim 1, wherein the memory access latency estimation system further comprises a third monitor, and a plurality of fourth monitors, and the method further comprises:
measuring, by the third monitor, a second access latency of a third access operation of a second memory, wherein the second memory comprises a dynamic random-access memory;
measuring, by the plurality of fourth monitors, a plurality of third indexes of the second memory corresponding to the third access operation;
using, by the processor, the plurality of updated first coefficients and the plurality of third indexes to perform a third weighted calculation to generate a third estimated latency;
adjusting, by the processor, the plurality of updated first coefficients to generate a plurality of second coefficients;
using, by the processor, the plurality of second coefficients and the plurality of third indexes to perform the third weighted calculation to adjust the third estimated latency for the third estimated latency to approximate the second access latency;
storing, by the processor, a relationship between the plurality of updated first coefficients corresponding to the first memory and the plurality of second coefficients corresponding to the second memory; and
estimating, by the processor, a group of coefficients corresponding to the second memory according to another group of coefficients corresponding to the first memory and the relationship;
wherein the number and the types of the plurality of first indexes are the same as number and types of the plurality of third indexes.

### Claim 13

A memory access latency estimation system, comprising:
a first monitor configured to measure a first access latency of a first access operation of a first memory, wherein the first memory comprises a dynamic random-access memory;
a plurality of second monitors configured to measure a plurality of first indexes of the first memory corresponding to the first access operation; and
a hardware-implemented processor configured to use a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjust the plurality of first coefficients to generate a plurality of updated first coefficients using a machine learning model implemented in hardware circuitry of the processor in order to use the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and use the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation;
wherein the processor comprises a member selected from a group comprising a central processing unit (CPU), a graphic processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application specific integrated circuit (ASIC), a deep learning processing unit (DPU), a vector processing unit (VPU), and a microprocessor, number and types of the plurality of first indexes are the same as number and types of the plurality of second indexes, the plurality of second indexes are corresponding to the second access operation, and the first access operation precedes the second access operation.

### Claim 14 (depends on 13)

The memory access latency estimation system of claim 13, further comprising:
a third monitor configured to measure a second access latency of a third access operation of a second memory, wherein the second memory comprises a dynamic random-access memory; and
a plurality of fourth monitors configured to measure a plurality of third indexes of the second memory corresponding to the third access operation;
wherein the processor is further configured to use the plurality of updated first coefficients and the plurality of third indexes to perform a third weighted calculation to generate a third estimated latency, adjust the plurality of updated first coefficients to generate a plurality of second coefficients, use the plurality of second coefficients and the plurality of third indexes to perform the third weighted calculation to adjust the third estimated latency for the third estimated latency to approximate the second access latency, store a relationship between the plurality of updated first coefficients corresponding to the first memory and the plurality of second coefficients corresponding to the second memory, and estimate a group of coefficients corresponding to the second memory according to another group of coefficients corresponding to the first memory and the relationship; and
the number and the types of the plurality of first indexes are the same as a number and types of the plurality of third indexes.

### Claim 15

A memory access latency estimation method of a memory access latency estimation system, the memory access latency estimation system comprising a plurality of first monitors, a plurality of second monitors, and a processor, the processor being hardware-implemented, the processor comprising a member selected from a group comprising a central processing unit (CPU), a graphic processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application specific integrated circuit (ASIC), a deep learning processing unit (DPU), a vector processing unit (VPU), and a microprocessor, the memory access latency estimation method comprising:
measuring, by the plurality of first monitors, a plurality of first indexes of a first dynamic random-access memory;
measuring, by the plurality of second monitors, a plurality of second indexes of a second dynamic random-access memory;
obtaining, by the processor, a relationship between the plurality of first indexes of the first dynamic random-access memory and the plurality of second indexes of the second dynamic random-access memory; and
generating, by the processor, a plurality of second coefficients for the second dynamic random-access memory according to the relationship and a plurality of first coefficients of the first dynamic random-access memory;
wherein the plurality of second coefficients are used to estimate an access latency of the second dynamic random-access memory, and number and the types of the plurality of first indexes are the same as number and types of the plurality of second indexes.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the plurality of second coefficients and a group of indexes of the second dynamic random-access memory are used to perform a weighted calculation to estimate the access latency of the second dynamic random-access memory.