# US 12,769,460 B2 · Two-stage emergency data storing operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,769,460 B2 - Document ID: US12769460B2 - Status: Granted - Kind: B2 - Application number: 19/217,243 - Filed: 2025-05-23 - Published: 2025-09-11 - Granted: 2026-10-20 - Earliest claimed: 2022-11-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Steffen Buch; Marco Redaelli - Web page: https://patentgrep.com/patent/US12769460B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage. ## Claims ### Claim 1 A memory device, comprising: one or more components configured to: read a mode register bit of the memory device, wherein a first state of the mode register bit indicates to perform a first data storing operation that includes a first stage and a second stage, wherein a second state of the mode register bit indicates to perform a second data storing operation that includes only one of the first stage or the second stage, and wherein the first stage includes storing data prior to the memory device experiencing a power loss, and the second stage includes storing data and metadata prior to the memory device experiencing the power loss; and initiate the first data storing operation or the second data storing operation based on the mode register bit. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first stage includes an emergency power fail operation and the second stage includes a forced quiescence operation. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the one or more components are further configured to: detect a power loss notification signal that indicates a power loss condition of the memory device, wherein reading the mode register bit is based on detecting the power loss notification signal. ### Claim 4 (depends on 1) The memory device of claim 1, wherein, when the mode register bit is in the second state, the one or more components are further configured to: read an additional mode register bit, wherein a first state of the additional mode register bit indicates that the first stage is enabled, and wherein a second state of the additional mode register bit indicates that the second stage is enabled. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the one or more components are further configured to: initiate the second data storing operation including the first stage or the second stage based on the mode register bit and the additional mode register bit. ### Claim 6 (depends on 1) The memory device of claim 1, wherein, when the mode register bit is in the first state, the one or more components are further configured to: perform the first stage of the first data storing operation; and initiate the second stage of the first data storing operation based on completing the first stage prior to a first time and based on having enough power to continue with the second stage. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the one or more components are configured to perform the first data storing operation or the second data storing operation using power received from one or more capacitors associated with the memory device. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the one or more components are configured to perform the first data storing operation or the second data storing operation using one or more voltages that supply power to the memory device. ### Claim 9 A system, comprising: a power component configured to transmit a signal, to a memory device, that indicates a power loss condition; and the memory device, wherein the memory device is configured to: read, based on the signal, a mode register bit of the memory device, wherein a first state of the mode register bit indicates to perform a first data storing operation that includes a first stage and a second stage, wherein a second state of the mode register bit indicates to perform a second data storing operation that includes only one of the first stage or the second stage, and wherein the first stage includes storing data prior to the memory device experiencing a power loss, and the second stage includes storing data and metadata prior to the memory device experiencing the power loss; and initiate the first data storing operation or the second data storing operation based on the mode register bit and the signal. ### Claim 10 (depends on 9) The system of claim 9, wherein the first stage includes an emergency power fail operation and the second stage includes a forced quiescence operation. ### Claim 11 (depends on 9) The system of claim 9, wherein, when the mode register bit is in the second state, the memory device is further configured to: read an additional mode register bit, wherein a first state of the additional mode register bit indicates that the first stage is enabled, and wherein a second state of the additional mode register bit indicates that the second stage is enabled. ### Claim 12 (depends on 11) The system of claim 11, wherein the memory device is further configured to: initiate the second data storing operation including the first stage or the second stage based on the mode register bit and the additional mode register bit. ### Claim 13 (depends on 9) The system of claim 9, wherein, when the mode register bit is in the first state, the memory device is further configured to: perform the first stage of the first data storing operation; and initiate the second stage of the first data storing operation based on completing the first stage prior to a first time. ### Claim 14 A method performed by a memory device, comprising: reading a mode register bit, wherein a first state of the mode register bit indicates to perform a first data storing operation that includes a first stage and a second stage, wherein a second state of the mode register bit indicates to perform a second data storing operation that includes only one of the first stage or the second stage, and wherein the first stage includes storing data prior to the memory device experiencing a power loss, and the second stage includes storing data and metadata prior to the memory device experiencing the power loss; and initiating the first data storing operation or the second data storing operation based on the mode register bit. ### Claim 15 (depends on 14) The method of claim 14, wherein the first stage includes an emergency power fail operation and the second stage includes a forced quiescence operation. ### Claim 16 (depends on 14) The method of claim 14, further comprising detecting a power loss condition or a standard shut-down condition of the memory device, wherein reading the mode register bit comprises reading the mode register bit based on detecting the power loss condition or the standard shut-down condition of the memory device. ### Claim 17 (depends on 14) The method of claim 14, further comprising detecting a power loss notification signal that indicates a power loss condition of the memory device, wherein reading the mode register bit is based on detecting the power loss notification signal. ### Claim 18 (depends on 14) The method of claim 14, wherein the mode register bit is in the second state, the method further comprising: reading an additional mode register bit, wherein a first state of the additional mode register bit indicates that the first stage is enabled, and wherein a second state of the additional mode register bit indicates that the second stage is enabled. ### Claim 19 (depends on 14) The method of claim 14, wherein the first data storing operation or the second data storing operation is performed using power received from one or more capacitors associated with the memory device. ### Claim 20 (depends on 14) The method of claim 14, wherein the first data storing operation or the second data storing operation is performed using one or more voltages that supply power to the memory device.