US 12,765,427 B2Granted

Integrated circuit(IC) package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce die-substrate clearance

AssigneeQUALCOMM Incorporated

InventorsAshish Alawani, Abhishek Shrikant Agarwal, Heun Gun Shin

Life of this patent

Estimating the term…

Loading patent…

Abstract

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).

Claims16

Dependent claims

An integrated circuit (IC) package, comprising:

a die comprising a plurality of die interconnects;
and
a substrate comprising a lower metallization layer extending in a first direction, the lower metallization layer comprising a plurality of metal interconnects, the plurality of metal interconnects comprising:
a first pad having a first surface and a second surface opposite the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction;
and
a second pad coupled to the first surface, the second pad having a second cross-sectional area extending in the first direction less than the first cross-sectional area;
and
a solder joint coupled to the second pad and a first die interconnect of the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction less than the first cross-sectional area, the second cross-sectional area is at least equal to the third cross-sectional area;
wherein the substrate further comprises:
an upper metallization layer extending in the first direction, the upper metallization layer comprising a second plurality of metal interconnects, the second plurality of metal interconnects comprising:
a second first pad having a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction;
and
wherein the IC package further comprises:
a second second pad extending in the first direction and adjacent to the third surface, the second second pad having a fifth cross-sectional area extending in the first direction and less than the fourth cross-sectional area;
and
a second solder joint coupled to the second second pad and a second die interconnect of the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction and less than the fourth cross-sectional area, the sixth cross-sectional area is less than or equal to the fifth cross-sectional area.

13 more elements

A method for fabricating a substrate, comprising:

forming a die comprising a plurality of die interconnects;
forming the substrate comprising a lower metallization layer extending in a first direction, the lower metallization layer comprising a plurality of metal interconnects, the plurality of metal interconnects comprising:
a first pad having a first surface and a second surface opposite the first surface in a second direction orthogonal to the first direction, the first pad having a first cross-sectional area extending in the first direction;
forming a second pad coupled to the first surface, the second pad having a second cross-sectional area extending in the first direction less than the first cross-sectional area;
and
coupling a solder joint to the second pad and a first die interconnect of the plurality of die interconnects, the first die interconnect having a third cross-sectional area extending in the first direction less than the first cross-sectional area, the second cross-sectional area is at least equal to the third cross-sectional area;
wherein the substrate further comprises:
an upper metallization layer extending in the first direction, the upper metallization layer comprising a second plurality of metal interconnects, the second plurality of metal interconnects comprising:
a second first pad having a fourth cross-sectional area extending in the first direction and a third surface extending in the first direction;
and
wherein the method further comprises:
forming a second second pad extending in the first direction and adjacent to the third surface, the second second pad having a fifth cross-sectional area extending in the first direction and less than the fourth cross-sectional area;
and
coupling a second solder joint to the second second pad and a second die interconnect of the plurality of die interconnects, the second die interconnect having a sixth cross-sectional area extending in the first direction and less than the fourth cross-sectional area, the sixth cross-sectional area is less than or equal to the fifth cross-sectional area.

11 more elements

Dependencies are inferred from the claim text.