# US 12,765,425 B2 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 12,765,425 B2
- Document ID: US12765425B2
- Status: Granted
- Kind: B2
- Application number: 18/463,792
- Filed: 2023-09-08
- Published: 2024-06-13
- Granted: 2026-10-13
- Earliest claimed: 2022-12-12
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Yuki Sato; Tsukasa Konno
- Web page: https://patentgrep.com/patent/US12765425B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 76/60: Seals
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes: a substrate; a first semiconductor chip; a first bonding pad; a second semiconductor chip arranged between the substrate and the first semiconductor chip; a second bonding pad; a first insulating film; a bonding wire that connects the substrate, the first bonding pad, and the second bonding pad; and a sealing resin that seals at least the first semiconductor chip, the second semiconductor chip, and the bonding wire. The second semiconductor chip includes a first surface that faces the substrate, and a second opposite surface. The second surface includes a first bonding region where the second bonding pad and the first insulating film are arranged, and a first lamination region that has a first low-level surface formed lower than a surface of the first insulating film, the first semiconductor chip arranged on or above at least a part of the first low-level surface.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate that includes an external terminal;
a first semiconductor chip on or above which a first bonding pad is arranged;
a second semiconductor chip that is arranged between the substrate and the first semiconductor chip, the second semiconductor chip on or above which a second bonding pad and a first insulating film being arranged;
a bonding wire that connects the substrate, the first bonding pad, and the second bonding pad; and
a sealing resin that seals at least the first semiconductor chip, the second semiconductor chip, and the bonding wire, wherein:
the second semiconductor chip includes a first surface that faces the substrate, and a second surface on an opposite side of the first surface; and
the second surface includes
a first bonding region where the second bonding pad and the first insulating film are arranged, and
a first lamination region that has a first low-level surface formed that being lower than a surface of the first insulating film, the first semiconductor chip being arranged on or above at least a part of the first low-level surface.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the surface of the first insulating film is formed that being higher than a surface of the second bonding pad.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein:
the first semiconductor chip includes a third surface that faces the substrate across the second semiconductor chip; and
the semiconductor device further comprises
an adhesion layer that performs adhesion between at least a part of the first lamination region on the second surface and at least a part of the third surface.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein:
a second insulating film is further arranged on or above the first semiconductor chip;
the first semiconductor chip includes a third surface that faces the substrate across the second semiconductor chip, and a fourth surface on an opposite side of the third surface; and
the fourth surface includes
a second bonding region where the first bonding pad and the second insulating film are arranged, and
a second lamination region that has a second low-level surface formed that being lower than a surface of the second insulating film, a third semiconductor chip being arranged on or above at least a part of the second low-level surface.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein:
the second surface has a rectangular shape; and
the first bonding region is positioned that being closer to one side of two facing sides of the rectangular shape than to the other side.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein
the first bonding region abuts on the one side.