Semiconductor device and method for manufacturing the same
AssigneeKioxia Corporation
InventorYasuhiro Uchiyama
Life of this patent
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Abstract
According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.
Claims18
A semiconductor device comprising:
- a first substrate;
- a first transistor provided on the first substrate;
- a memory cell array, provided above the first transistor, that includes a plurality of electrode layers stacked in a first direction, a semiconductor layer provided above the plurality of electrode layers, and a metallic layer provided in contact with the semiconductor layer above the semiconductor layer;
- a first plug provided above the first transistor and electrically connected to the first transistor;
- and
- a metallic wiring layer provided in contact with the metallic layer and electrically connected to the first plug,
- wherein the metallic layer includes a first surface and a second surface that is opposite the first surface, the first surface in contact with the semiconductor layer and the second surface in contact with the metallic wiring layer,
- the metallic wiring layer includes a first portion in direct contact with the metallic layer and a second portion separated from the metallic layer with an insulating film, and the first plug extends through the insulating film to contact the metallic wiring layer, and
- the metallic wiring layer is provided over the semiconductor layer.
A semiconductor device comprising:
- a first substrate;
- a first transistor provided on the first substrate;
- a memory cell array, provided above the first transistor, that includes a plurality of electrode layers stacked in a first direction, a semiconductor layer provided above the plurality of electrode layers, a memory pillar extending through the plurality of electrode layers in the first direction, a trench dividing the plurality of electrode layers into a plurality of parts in a second direction intersecting the first direction, and a metallic layer provided in contact with the semiconductor layer above the semiconductor layer;
- a first plug provided above the first transistor and electrically connected to the first transistor;
- and
- a metallic wiring layer provided in contact with the metallic layer and electrically connected to the first plug,
- wherein the metallic layer includes a first surface and a second surface that is opposite the first surface, the first surface in contact with the semiconductor layer and the second surface in contact with the metallic wiring layer,
- the metallic layer contacts the metallic wiring layer above the memory pillar or the trench at multiple locations wherein the multiple locations are laterally aligned along the second surface of the metallic layer, and
- wherein the metallic wiring layer includes a first portion in direct contact with the metallic layer and a second portion separated from the metallic layer with an insulating film, and the first plug extends through the insulating film to contact the metallic wiring layer.
Dependencies are inferred from the claim text.