Semiconductor package structure and manufacturing method

A method for manufacturing a semiconductor package structure, comprising:

• providing a first base plate, wherein the first base plate is provided with a first surface;
• forming a first chip stack body on the first base plate, wherein the first chip stack body comprises a plurality of first semiconductor chips that are successively stacked onto one another in a direction perpendicular to the first base plate, and the first chip stack body is electrically connected to the first surface of the first base plate;
• forming an interposer layer on the first chip stack body, wherein the interposer layer is provided with a first interconnection surface, the first interconnection surface is provided with a first interconnection region and a second interconnection region, and the first interconnection region is electrically connected to the first base plate;
• forming a plurality of first pads on the first interconnection region;
• and forming a plurality of second pads on the second interconnection region, wherein a number of the plurality of second pads is greater than a number of the plurality of first pads, and an area of each of the plurality of second pads is less than an area of each of the plurality of first pads;
• and
• forming a molding layer, wherein the molding layer is configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate, wherein the first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer, wherein there is a preset height between the first interconnection region and a top surface of the molding layer on the second interconnection region, and a first material layer is formed on a sidewall between the first interconnection region and the top surface of the molding layer on the second interconnection region.

A semiconductor package structure, comprising:

• a first base plate provided with a first surface;
• a first chip stack body located on the first base plate, wherein the first chip stack body comprises a plurality of first semiconductor chips that are successively stacked onto one another in a direction perpendicular to the first base plate, and the first chip stack body is electrically connected to the first surface of the first base plate;
• an interposer layer located on the first chip stack body, wherein the interposer layer is provided with a first interconnection surface, the first interconnection surface is provided with a first interconnection region and a second interconnection region, and the first interconnection region is electrically connected to the first base plate;
• and
• a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate, wherein the first interconnection region is unsealed by the molding layer, the second interconnection region is sealed by the molding layer, and a first material layer is formed on a sidewall between the first interconnection region and a top surface of the molding layer on the second interconnection region;
• a second package structure, wherein the second package structure comprises a first solder ball, and the first solder ball is electrically connected to the first interconnection region,
• wherein there is a preset height between the first interconnection region and the top surface of the molding layer on the second interconnection region, and a height of the first solder ball is greater than the preset height.