# US 12,765,416 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 12,765,416 B2
- Document ID: US12765416B2
- Status: Granted
- Kind: B2
- Application number: 17/840,164
- Filed: 2022-06-14
- Published: 2022-12-22
- Granted: 2026-10-13
- Earliest claimed: 2021-06-16
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Naoya Nouzu
- Web page: https://patentgrep.com/patent/US12765416B2

## CPC

- H10W 90/00: Package configurations
- H10D 62/378: {Contact regions to the substrate regions}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes: a semiconductor chip including a first main surface on one side and a second main surface on the other side; a pn junction portion extending along the first main surface and formed inside the semiconductor chip; a trench configured to penetrate the pn junction portion from the first main surface and partition an element region in the semiconductor chip; an insulating film configured to cover a side wall and a bottom wall of the trench; and an embedded electrode embedded in the trench via the insulating film, wherein the bottom wall of the trench includes a protrusion protruding from a lower end of the insulating film toward an inner upper side of the insulating film in a depth direction of the trench.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor chip including a first main surface on one side and a second main surface on the other side;
a pn junction portion extending along the first main surface and formed inside the semiconductor chip;
a trench configured to penetrate the pn junction portion from the first main surface and partition an element region in the semiconductor chip;
an insulating film configured to cover a side wall and a bottom wall of the trench; and
an embedded electrode embedded in the trench via the insulating film,
wherein the bottom wall of the trench includes a protrusion protruding from a lower end of the insulating film toward an inner upper side of the insulating film in a depth direction of the trench, and
wherein a thickness of the insulating film in a direction intersecting the depth direction of the trench is 2 μm or more and 6 μm or less.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the insulating film includes a contact hole that selectively exposes the bottom wall of the trench, and
wherein the embedded electrode includes a contact portion connected to the semiconductor chip via the contact hole.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the semiconductor chip includes a recess continuous with the contact hole, and
wherein the contact portion is formed in the recess via the contact hole.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the contact portion includes a bottom portion extending along the bottom wall of the trench, and a side portion extending upward from the bottom portion and crossing a boundary portion between the insulating film and the bottom wall of the trench.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the side portion of the contact portion has a curved shape in a cross-sectional view.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the direction intersecting the depth direction of the trench is orthogonal to the depth direction of the trench.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein the insulating film is formed of:
a first film portion including a first portion and a second portion, and
a second film portion including a third portion and a fourth portion, and having a lower density than the first film portion; and
wherein the third portion, the first portion, the fourth portion and the second portion, each of which extends in the depth direction of the trench, are formed sequentially from the embedded electrode toward the side wall of the trench in the direction intersecting the depth direction of the trench.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein at least the side wall and the bottom wall of the trench are covered with the first film portion of the insulating film.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the protrusion is formed to protrude into an interior of the first film portion that covers the bottom wall of the trench.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the trench includes an annular trench that surrounds the element region,
wherein the insulating film includes an annular portion formed on a side wall of the annular trench along a circumferential direction of the annular trench in a plan view, and
wherein the protrusion is formed to overlap with the annular portion, along the circumferential direction of the annular portion of the insulating film in a plan view.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
a first step of forming a trench penetrating a pn junction portion and partitioning an element region in a semiconductor layer by selectively etching the semiconductor layer, which includes a first main surface on one side and a second main surface on the other side and in which the pn junction portion extending along the first main surface is formed, and forming a semiconductor wall portion erected on a bottom wall of the trench by using a part of the semiconductor layer and facing a side wall of the trench across a space;
a second step of forming a first insulating film along the side wall and the bottom wall of the trench by thermal oxidation, modifying the semiconductor wall portion into an insulator by the thermal oxidation, and forming an insulator wall portion facing the first insulating film on the side wall of the trench across the space;
a third step of forming a side wall insulating film including the first insulating film, an embedded insulating film, the insulator wall portion and a second insulating film on the side wall of the trench, and a bottom wall insulating film including the first insulating film and the second insulating film on the bottom wall of the trench, by depositing an insulating material in the trench to form the embedded insulating film back-filling the space and the second insulating film extending along the side wall of the insulator wall portion and the bottom wall of the trench on the opposite side of the space; and
a fourth step of forming an embedded electrode back-filling the trench by depositing a conductive material in the trench,
wherein a thickness of the side wall insulating film in a direction intersecting a depth direction of the trench is 2 μm or more and 6 μm or less.

### Claim 12 (depends on 11)

The method of claim 11, wherein the third step includes depositing the insulating material by a CVD method using a TEOS gas.

### Claim 13 (depends on 11)

The method of claim 11, wherein a thickness of the semiconductor wall portion is 1 μm or less.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
a first step of forming a trench group including at least three annular trenches arranged concentrically with each other, penetrating a pn junction portion and partitioning an element region in a semiconductor layer by selectively etching the semiconductor layer, which includes a first main surface one side and a second main surface on the other side and in which the pn junction portion extending along the first main surface is formed, wherein the trench group includes a main trench and a plurality of sub-trenches arranged inside and outside the main trench and having a smaller width than the main trench;
a second step of forming a first insulating film along a side wall and a bottom wall of each of the annular trenches belonging to the trench group by thermal oxidation, modifying a portion of the semiconductor layer sandwiched between the annular trenches adjacent each other into an insulator by the thermal oxidation, and forming a boundary insulating film forming a boundary between the annular trenches adjacent each other;
a third step of forming a side wall insulating film including a second insulating film, the boundary insulating film, an embedded insulating film and the first insulating film on each of the inside and outside of the main trench and a furth including the first insulating film and the second insulating film on the bottom wall of the main trench, by depositing an insulating material in the trench group after the second step to form the embedded insulating film back-filling the sub-trenches and the second insulating film extending along an inner surface of the main trench;
a fourth step of forming a contact hole exposing a part of the semiconductor layer in the bottom wall of the main trench by selectively removing the bottom wall insulating film in the main trench; and
a fifth step of forming an embedded electrode back-filling the main trench and connected to the semiconductor layer via the contact hole by depositing a conductive material in the main trench,
wherein a thickness of the side wall insulating film in a direction intersecting a depth direction of the trench group is 2 μm or more and 6 μm or less.

### Claim 15 (depends on 14)

The method of claim 14, wherein a thickness of the boundary insulating film in the direction intersecting the depth direction of the trench group is 1 μm or less.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first step includes forming the same number of the sub-trenches inside and outside of the main trench.

### Claim 17 (depends on 14)

The method of claim 14, wherein the first step includes forming a plurality of the sub-trenches on each of the inside and outside of the main trench, respectively.

### Claim 18 (depends on 14)

The method of claim 14, wherein a width of the main trench is 2.5 μm or more and 3 μm or less, and a width of the sub-trenches is 1 μm or more and 1.5 μm or less.