Interconnection structure and semiconductor package including the same

A method of manufacturing an interconnection structure, comprising:

• providing a lower dielectric layer;
• forming a first hardmask layer including a dielectric material having an etch selectivity with respect to the lower dielectric layer and conformally covering an upper surface of the lower dielectric layer;
• forming a first hardmask pattern by etching the first hardmask layer using a first mask pattern as a first mask;
• forming a lower hole by etching the lower dielectric layer using the first mask pattern and the first hardmask pattern as a second mask;
• forming a lower conductive pattern covering the lower hole;
• providing an internal dielectric layer on the lower conductive pattern and the first hardmask pattern;
• forming a second hardmask layer including a dielectric material having an etch selectivity with respect to the internal dielectric layer and covering an upper surface of the internal dielectric layer;
• forming a second hardmask pattern by etching the second hardmask layer using a second mask pattern as a third mask;
• forming a via hole and trenches in the internal dielectric layer by etching the internal dielectric layer using the second mask pattern and the second hardmask pattern as masks;
• and
• forming an interconnection pattern covering the via hole and the trenches,
• wherein the interconnection pattern includes a via part covering the via hole, a pad part vertically overlapping the via part, and a line part extending from the pad part,
• wherein a bottom surface of the pad part, a bottom surface of the line part, and a lateral surface of the via part are in contact with the internal dielectric layer,
• wherein the via hole and the trenches are defined by the internal dielectric layer such that the internal dielectric layer surrounds the via part, the pad part, and the line part in a lateral direction, and
• wherein the internal dielectric layer is a single internal dielectric layer.