Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip that includes a first silicon substrate, a first semiconductor element formed on an active surface of the first silicon substrate, and a first circuit layer disposed on the active surface of the first silicon substrate;
• a first redistribution layer disposed on an active surface of the first semiconductor chip and coupled to the first circuit layer;
• a second redistribution layer disposed on an inactive surface of the first semiconductor chip;
• a first through via that vertically penetrates the first semiconductor chip and connects the first redistribution layer and the second redistribution layer to each other;
• and
• a plurality of pads disposed on the first redistribution layer,
• wherein the first circuit layer includes:
• a first device interlayer dielectric layer that covers the active surface of the first silicon substrate;
• and
• a first circuit wiring pattern provided in the first device interlayer dielectric layer,
• wherein the first through via is spaced apart from the first circuit wiring pattern.

A semiconductor package, comprising:

• a package substrate;
• and
• a chip package mounted on the package substrate,
• wherein the chip package includes:
• a semiconductor chip that includes a silicon substrate and a circuit wiring pattern on the silicon substrate, the silicon substrate having a semiconductor element formed on an active surface of the silicon substrate, and the circuit wiring pattern being connected to the semiconductor element;
• a first redistribution layer disposed on a first surface of the semiconductor chip, the first surface being directed toward the package substrate;
• a second redistribution layer disposed on a second surface of the semiconductor chip, the second surface being opposite to the first surface;
• and
• a plurality of through vias that vertically penetrate the semiconductor chip and connect the first redistribution layer and the second redistribution layer to each other,
• wherein the plurality of through vias are positioned between the circuit wiring pattern and an outer edge of the silicon substrate, and
• wherein a distance from the outer edge of the silicon substrate to a conductive pattern of the first redistribution layer is less than a distance from the outer edge of the silicon substrate to the circuit wiring pattern.