Semiconductor structure and method manufacturing the same

A semiconductor structure, comprising:

• a plurality of semiconductor chips, each comprising:
• a first tier, comprising at least one first integrated circuit component with first through vias disposed therein;
• a second tier, disposed on and electrically coupled to the first tier and comprising at least one second integrated circuit component with second through vias disposed therein;
• and
• a plurality of conductive elements, disposed over the second tier, wherein the second tier is between the first tier and the plurality of conductive elements;
• an insulating encapsulation, laterally encapsulating the plurality of semiconductor chips;
• a redistribution circuit structure, disposed over the insulating encapsulation and electrically coupled to the plurality of semiconductor chips;
• a plurality of conductive terminals, disposed on and electrically coupled to the redistribution circuit structure, wherein the redistribution circuit structure is between the insulating encapsulation and the plurality of conductive terminals;
• a circuit substrate, wherein the circuit substrate is mounted to and electrically coupled to the redistribution circuit structure through the plurality of conductive terminals;
• and
• a heat dissipating element, disposed over the plurality of semiconductor chips and comprising a plurality of microstructures, wherein the plurality of microstructures are in physical contact with the plurality of semiconductor chips, and the plurality of microstructures penetrate through a thermal interface material disposed on the insulating encapsulation and further extending onto the plurality of semiconductor chips,
• wherein in a cross section of the semiconductor structure along the heat dissipating element and the plurality of semiconductor chips, the thermal interface material directly contacts a planar bottom surface of the heat dissipating element that extends beyond the thermal interface material.

A semiconductor structure, comprising:

• a plurality of semiconductor chips, each comprising:
• a first tier, comprising a first integrated circuit component;
• and
• a second tier, over and electrically coupled to the first tier and comprising a second integrated circuit component;
• an insulating encapsulation, laterally encapsulating the plurality of semiconductor chips;
• a redistribution circuit structure, disposed over the insulating encapsulation and electrically coupled to the plurality of semiconductor chips;
• and
• a heat dissipating element, disposed over the plurality of semiconductor chips, wherein the heat dissipating element comprises a lid vertically overlapped with the plurality of semiconductor chips, a ring structure connecting to the lid and vertically extending away from the lid, and a plurality of microstructures connected to the lid and further protruding from the lid towards the plurality of semiconductor chips, wherein the plurality of microstructures are in physical contact with the plurality of semiconductor chips, and the plurality of microstructures penetrate through a thermal interface material disposed between the lid and the plurality of semiconductor chips, wherein the ring structure is laterally next to the plurality of semiconductor chips and the redistribution circuit structure,
• wherein in a cross section of the semiconductor structure along the heat dissipating element and the plurality of semiconductor chips, the thermal interface material directly contacts a lower surface of the lid that is entirely planar within the ring structure.