# US 12,765,401 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 12,765,401 B2
- Document ID: US12765401B2
- Status: Granted
- Kind: B2
- Application number: 18/380,937
- Filed: 2023-10-17
- Published: 2024-08-22
- Granted: 2026-10-13
- Earliest claimed: 2023-02-22
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Hsih-Yang Chiu
- Web page: https://patentgrep.com/patent/US12765401B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an interposer, a conductive via, an insulation layer, and a first electronic component. The interposer has a first surface and a second surface opposite to the first surface. The conductive via extends between the first surface and the second surface of the interposer. The insulation layer separates the conductive via from the interposer. The first electronic component is disposed on the second surface and electrically connected to the conductive via.

## Claims

### Claim 1

A semiconductor device, comprising:
an interposer having a first surface and a second surface opposite to the first surface, wherein the interposer defines a first cavity and a second cavity extending between the first surface and the second surface;
a through-insulation via (TIV) disposed within the first cavity;
a first electronic component disposed on the second surface of the interposer and electrically connected to the TIV;
a second electronic component disposed within the second cavity at a position that the second electronic component is embedded within the interposer;
an insulation layer disposed within the first cavity and penetrating the interposer; and
an encapsulant disposed within the second cavity and encapsulating the second electronic component, wherein the encapsulant fully penetrates the interposer;
wherein the first cavity and the second cavity are recessed from the first surface of the interposer to define a bottom of the first cavity and a bottom of the second cavity above the second surface of the interposer;
wherein a depth of the first cavity is equal to a depth of the second cavity.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first protection layer covering the insulation layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a conductive pillar disposed within the second cavity and electrically connected to the second electronic component, wherein the encapsulant is only disposed in the second cavity while the first cavity is free of the encapsulant.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the conductive pillar is encapsulated by the encapsulant.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second protection layer disposed on the second surface of the interposer, wherein the second protection layer has a lower surface coplanar with the first surface of the interposer and an upper surface coplanar with an upper surface of the encapsulant.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the lower surface of the second protection layer is substantially coplanar with a fourth surface of the TIV.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third electronic component disposed on the second surface of the interposer, wherein the third electronic component is connected to the interposer through an adhesive layer, wherein the third electronic component is free from overlapping the first cavity and the second cavity of the interposer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the third electronic component is free from overlapping the first cavity and the second cavity of the interposer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising;
a mother board facing the first surface of the interposer; and
a conductive wire electrically connecting the third electronic component and the mother board.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the TIV is electrically connected to the mother board.