# US 12,765,392 B2 · Semiconductor package and method of manufacturing the semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,765,392 B2 - Document ID: US12765392B2 - Status: Granted - Kind: B2 - Application number: 18/515,797 - Filed: 2023-11-21 - Published: 2024-06-27 - Granted: 2026-10-13 - Earliest claimed: 2022-12-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Junghoon Kang; Unbyoung Kang; Jinsu Kim; Seungwan Shin; Byoungwook Jang - Web page: https://patentgrep.com/patent/US12765392B2 ## CPC - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 46/401: {for identification or tracking} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings. ## Claims ### Claim 1 A semiconductor package, comprising: a lower redistribution wiring layer having a first region and a second region adjacent the first region, the lower redistribution wiring layer including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern in a marking layer of the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are in the marking layer and exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer including a layer of second redistribution wirings electrically connected to the plurality of vertical conductive structures, wherein the layer of second redistribution wiring is on the sealing member and the marking layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein an upper surface of the marking pattern is coplanar with the upper surface of the sealing member. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein an upper surface of the seed layer pad is coplanar with or lower than the upper surface of the sealing member. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the sealing member is on a side surface of the marking pattern. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the marking pattern includes a first seed layer and a second seed layer stacked on the first seed layer. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the first seed layer includes copper, and the second seed layer includes titanium. ### Claim 7 (depends on 5) The semiconductor package of claim 5, wherein the seed layer pads respectively comprise the first seed layer and the second seed layer stacked on the first seed layer, or wherein the seed layer pads respectively comprise the first seed layer. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the marking pattern has a thickness of about 0.1 micrometers (μm) to about 0.5 μm. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the marking pattern is attached on a backside of the semiconductor chip by an adhesive film, wherein the backside of the semiconductor chip is opposite the lower redistribution wiring layer. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip is a first semiconductor chip of a first package, and further comprising: a second package on the upper redistribution wiring layer, wherein the second package includes a package substrate and at least one second semiconductor chip stacked on the package substrate. ### Claim 11 A semiconductor package, comprising: a lower redistribution wiring layer including first redistribution wirings; a semiconductor chip on the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads faces the lower redistribution wiring layer; a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface; a plurality of vertical conductive structures penetrating the sealing member and electrically connected to the first redistribution wirings; a marking pattern in a marking layer on the second surface of the semiconductor chip; and an upper redistribution wiring layer including a layer of second redistribution wirings electrically connected to the plurality of vertical conductive structures, wherein the layer of second redistribution wiring is on the sealing member and the marking layer, wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member. ### Claim 12 (depends on 11) The semiconductor package of claim 11, further comprising: seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at the upper surface thereof. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein upper surfaces of the seed layer pads are coplanar with or lower than the upper surface of the sealing member. ### Claim 14 (depends on 12) The semiconductor package of claim 12, wherein the sealing member is on side surfaces of the seed layer pads. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein: the seed layer pads respectively comprise a first seed layer and a second seed layer stacked on the first seed layer, or the seed layer pads respectively comprise the first seed layer; and wherein the marking pattern comprises the first seed layer and the second seed layer. ### Claim 16 A semiconductor package, comprising: a lower redistribution wiring layer having a first region and a second region adjacent the first region, the lower redistribution wiring layer including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads faces the lower redistribution wiring layer; a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the second surface of the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings on the seed layer pads, wherein the sealing member is on a side surface of the marking pattern and is on side surfaces of the seed layer pads. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein the marking pattern includes a first seed layer and a second seed layer stacked on the first seed layer. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein the marking pattern includes a seed layer dummy pattern on the second surface of the semiconductor chip and a plurality of openings penetrating the seed layer dummy pattern to define an intaglio pattern. ### Claim 19 (depends on 16) The semiconductor package of claim 16, wherein the marking pattern is attached to the second surface of the semiconductor chip by an adhesive film. ### Claim 20 (depends on 19) The semiconductor package of claim 19, wherein the adhesive film at least partially fills a plurality of openings that extend through the marking pattern.