Semiconductor package including a laser mark area comprising portions of a redistribution level layer

A semiconductor package comprising:

• an encapsulation layer encapsulating at least one semiconductor chip;
• and
• a redistribution level layer disposed on the encapsulation layer, the redistribution level layer comprising a redistribution conductive layer and a redistribution insulating layer insulating the redistribution conductive layer;
• a laser mark insulating layer located on the redistribution conductive layer and the redistribution insulating layer;
• and
• a laser mark area comprising those portions of the redistribution conductive layer, the redistribution insulating layer, and the laser mark insulating layer that are formed within a first region of the semiconductor package with respect to a top down view, the redistribution conductive layer comprising a laser mark metal layer, the redistribution insulating layer of the laser mark area comprising a plurality of mesh-type redistribution insulating patterns spaced apart from each other in a horizontal direction and surrounded by the laser mark metal layer, and the laser mark insulating layer of the laser mark area comprising a laser mark directly exposing the laser mark metal layer and at least some of the mesh-type redistribution insulating patterns,
• wherein the laser mark metal layer directly exposed by the laser mark comprises a first laser mark metal pattern having a first length in the horizontal direction and a second laser mark metal pattern having a second length in the horizontal direction greater than the first length, and
• wherein side surfaces of the redistribution conductive layer directly exposed by the laser mark directly contact side surfaces of the mesh-type redistribution insulating patterns directly exposed by the laser mark.

A semiconductor package comprising:

• a fan-in area in which a semiconductor chip is located;
• and a fan-out area comprising a package element surrounding the fan-in area and having an inner wiring layer;
• a package body level layer comprising a fan-in encapsulation layer sealing the semiconductor chip in the fan-in area;
• a first redistribution level layer disposed on a lower surface of the package body level layer and comprising a first redistribution conductive layer extending to the fan-out area and a first redistribution insulating layer insulating the first redistribution conductive layer;
• a second redistribution level layer disposed on an upper surface of the package body level layer, and comprising a second redistribution conductive layer extending to the fan-out area, and a second redistribution insulating layer insulating the second redistribution conductive layer;
• a laser mark insulating layer located on the second redistribution conductive layer and the second redistribution insulating layer;
• and
• a laser mark area comprising those portions of the second redistribution conductive layer, the second redistribution insulating layer, and the laser mark insulating layer that are formed within a first region of the semiconductor package with respect to a top down view, the second redistribution insulating layer of the laser mark area comprises a plurality of mesh-type redistribution insulating patterns spaced apart from each other in a horizontal direction, the laser mark insulating layer comprising a laser mark directly exposing the second redistribution conductive layer and the mesh-type redistribution insulating patterns,
• wherein side surfaces of the second redistribution conductive layer directly exposed by the laser mark directly contact side surfaces of the mesh-type redistribution insulating patterns directly exposed by the laser mark.