Transistors with selectively landed gate array

A semiconductor device, comprising:

• a plurality of transistors including a plurality of source regions and a plurality of gate electrodes;
• a first array of low-resistance plug material formed at a first plug layer on the plurality of transistors, with a gate subset of the first array formed on the plurality of gate electrodes and a source subset of the first array formed on the plurality of source regions;
• a second array of low-resistance plug material formed at a second plug layer on the first plug layer, with a gate subset of the second array formed vertically above the gate subset of the first array in a direction perpendicular to a surface of the first array and electrically connected to the plurality of gate electrodes, and a source subset of the second array formed vertically above the source subset of the first array in the direction perpendicular to the surface of the first array and electrically connected to the plurality of source regions;
• a gate pad metal formed at a first metal layer on the second plug layer and electrically connected to the gate subset of the second array;
• and
• a source pad metal formed at the first metal layer and electrically connected to the source subset of the second array.

A method of making a semiconductor device, comprising:

• forming, in a substrate, a plurality of transistors including a plurality of source regions and a plurality of gate electrodes;
• forming a first dielectric layer on the plurality of source regions and the plurality of gate electrodes;
• forming a first array of low-resistance material in the first dielectric layer, with a gate subset of the first array formed on the plurality of gate electrodes and a source subset of the first array formed on the plurality of source regions;
• forming a second dielectric layer on the first dielectric layer and on the first array;
• forming a second array of low-resistance material in the second dielectric layer, with a gate subset of the second array formed vertically above the gate subset of the first array in a direction perpendicular to a surface of the first dielectric layer and electrically connected to the plurality of gate electrodes, and a source subset of the second array formed vertically above the source subset of the first array in a direction perpendicular to the surface of the first dielectric layer and electrically connected to the plurality of source regions;
• forming a gate pad metal on the second dielectric layer and electrically connected to the gate subset of the second array;
• and
• forming a source pad metal on the second dielectric layer and electrically connected to the source subset of the second array.