# US 12,765,366 B2 · Semiconductor device with composite dielectric and method for fabricating the same

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- Number: US 12,765,366 B2
- Document ID: US12765366B2
- Status: Granted
- Kind: B2
- Application number: 18/631,399
- Filed: 2024-04-10
- Published: 2025-09-25
- Granted: 2026-10-13
- Earliest claimed: 2024-03-21
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Yuan-Yuan Lin
- Web page: https://patentgrep.com/patent/US12765366B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10P 14/6319: {Formation by plasma treatments, e.g. plasma oxidation of the substrate}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first interconnect structure disposed in a semiconductor substrate, first and second dielectric layers disposed over the semiconductor substrate, a second interconnect structure disposed in the first and second dielectric layers, and a third interconnect structure disposed in the semiconductor substrate. The first interconnect structure includes a first conductive line and a first manganese-containing layer. The second interconnect structure includes a second conductive line and a second manganese-containing layer. The third interconnect structure includes a third conductive line and a third manganese-containing layer. The third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure are made of a same material.

## Claims

### Claim 1

A semiconductor device, comprising:
a capacitor contact disposed over a semiconductor substrate;
a first dielectric layer disposed over the capacitor contact;
a patterned mask disposed over the first dielectric layer; and
a bottom capacitor electrode disposed over and electrically connected to the capacitor contact, wherein the bottom capacitor electrode comprises:
a base layer disposed between the capacitor contact and the first dielectric layer;
a surrounding portion disposed over the base layer and along sidewalls of the first dielectric layer and the patterned mask; and
a first interconnect portion disposed between the patterned mask and the base layer, wherein the first interconnect portion is substantially parallel to the base layer;
wherein the patterned mask is surrounded by the surrounding portion, wherein sidewalls of the patterned mask are substantially aligned with sidewalls of the first dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a source/drain region is formed in the semiconductor substrate and the capacitor contact is disposed over the source/drain region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a second dielectric layer disposed over the source/drain region, wherein the second dielectric layer comprises a bottom porous dielectric layer disposed over the source/drain region and a top porous dielectric layer disposed over the bottom porous dielectric layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a porosity of the top porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the capacitor contact is surrounded by the second dielectric layer.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the capacitor contact includes a conductive layer and a liner layer, wherein the conductive layer includes a vertical portion disposed over the semiconductor substrate and a horizontal portion disposed on the vertical portion.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a width of the vertical portion is less than a width of the horizontal portion.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, further comprising a bottom barrier layer formed over the source/drain region and disposed between the second dielectric layer and the capacitor contact.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the bottom barrier layer is made of at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the bottom capacitor electrode further comprises a second interconnect portion disposed in the first dielectric layer, and between the first interconnect portion and the base layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the second interconnect portion is substantially parallel to the first interconnect portion.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the base layer is made of at least one of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), and tantalum (Ta).