US 12,765,365 B2 · Integrated circuit device

Abstract

An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

Claims20

Dependent claims

An integrated circuit device comprising:

a source/drain contact insulation layer on a lower structure;
a source/drain contact via penetrating through the source/drain contact insulation layer;
an interconnect wiring insulation layer on the source/drain contact insulation layer, the interconnect wiring insulation layer including an interconnect wiring trench exposing a top surface of the source/drain contact via;
a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench, the first interconnect wiring layer including a first precursor;
and
a second interconnect wiring layer on the first interconnect wiring layer, the second interconnect wiring layer covering an upper portion of the sidewall of the interconnect wiring trench, and the second interconnect wiring layer including a second precursor, wherein
a crystal grain size of the second precursor is larger than a crystal grain size of the first precursor.

4 more elements

An integrated circuit device comprising:

a substrate including a fin-type active region protruding from a surface of the substrate;
a source/drain region on the fin-type active region;
a metal silicide layer in contact with a top surface of the source/drain region;
a gate line extending over the fin-type active region in a direction crossing the fin-type active region;
an insulation structure on the source/drain region, the metal silicide layer, and the gate line;
a source/drain contact penetrating through a first portion of the insulation structure in a vertical direction and connecting to the source/drain region through the metal silicide layer;
a gate contact penetrating through a second portion of the insulation structure in the vertical direction and connecting to the gate line;
an interconnect wiring pattern electrically connected to the source/drain contact or the gate contact;
and
a plurality of wiring structures on the interconnect wiring pattern and arranged at different levels in the vertical direction, wherein
the plurality of wiring structures include a plurality of wiring patterns,
at least one of the interconnect wiring pattern and the plurality of wiring patterns includes a first wiring layer and a second wiring layer covering a top surface of the first wiring layer,
the first wiring layer contains oxygen, and
the second wiring layer does not contain oxygen.

11 more elements

Dependencies are inferred from the claim text.

Integrated circuit device

Life of this patent

Integrated circuit device

Life of this patent

Abstract

Claims20